UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25428

Architecture Wizard, XtremeDSP Slice - Why does the Adder/Subtractor Architecture Wizard always have a clock input, even when no registers are selected, or why is ACASCREG, BCASCREG or MREG always set to '1' in the HDL?

Description

Why does the Adder/Subtractor Architecture Wizard always have a clock input, even when no registers are selected, (why is ACASCREG, BCASCREG or MREG always set to '1' in the HDL)? 

 

This can be seen with multiple configurations, but it is often found when creating combinatorial DSP48, or one that does not use the 3-stage pipeline.

Solution

This is a known bug in the XtremeDSP Slice Adder/Subtracter Architecture Wizard output. 

 

It is possible to work around this by inferring at DSP48E using HDL. 

 

This will ensure that the code is more portable as well as ensuring that the code implements a DSP48E. 

 

Combinatorial Adder Example Code: 

VHDL 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.NUMERIC_STD.ALL; 

 

entity add_sub_dsp48 is 

port ( A : in std_logic_vector (17 downto 0); 

B : in std_logic_vector (17 downto 0); 

P_OUT : out std_logic_vector (18 downto 0)); 

end add_sub_dsp48; 

 

architecture Behavioral of add_sub_dsp48 is 

 

-- These 2 lines can be commented out to let the Synthesis Tool 

-- decided if a DSP48 should be used. 

attribute use_dsp48 : string ; 

attribute use_dsp48 of P_OUT : signal is "yes"; 

 

begin 

-- An attribute is needed to used to infer a DSP48E. 

-- Type conversion needed because the DSP48E is a signed 2s complement component. 

-- If the input and output are defined as type SIGNED, then the conversion 

-- is not necessary. 

P_OUT <= STD_LOGIC_VECTOR(SIGNED(A) + SIGNED(B)); 

 

end Behavioral; 

 

 

For a list of alternative solutions to using the Architecture Wizard, see (Xilinx Answer 30101).

AR# 25428
Date Created 09/04/2007
Last Updated 08/14/2014
Status Active
Type General Article