Why does the Adder/Subtractor Architecture Wizard always have a clock input, even when no registers are selected, (why is ACASCREG, BCASCREG or MREG always set to '1' in the HDL)?
This can be seen with multiple configurations, but it is often found when creating combinatorial DSP48, or one that does not use the 3-stage pipeline.
This is a known bug in the XtremeDSP Slice Adder/Subtracter Architecture Wizard output.
It is possible to work around this by inferring at DSP48E using HDL.
This will ensure that the code is more portable as well as ensuring that the code implements a DSP48E.
Combinatorial Adder Example Code:
For a list of alternative solutions to using the Architecture Wizard, see (Xilinx Answer 30101).