MIG v1.72 - Twr violation occurs when the Address FIFO is empty and an Auto Refresh command is requested
Description
Keywords: MIG, DDR, DDR2, SDRAM, TWR, Violation, Auto Refresh, FIFO, empty
In the MIG v1.72 DDR/DDR2 SDRAM designs for Virtex-5, Twr violations occur when the Address FIFO is empty and there is an Auto Refresh request. How can I work around this issue?
Solution
In the Virtex-5 DDR/DDR2 SDRAM designs, when the address FIFO goes empty, there is an Auto Refresh request and the wtp_cnt_r or rtp_cnt_r counters are not yet decremented to zero, a Twr violation occurs at the memory. In the rtl, the state machine reaches the CTRL_COMMAND_WAIT state and the counters are not yet reduced to zeros during an Auto Refresh request. The state machine then issues a Precharge command to memory, which violates the Write to Precharge timing parameter.This issue is resolved in MIG v1.73 available with 9.2i IP Update 1. Please see (Xilinx Answer 25222) for information on downloading 9.2i IP Update 1 and (Xilinx Answer 25406) for information on the MIG v1.73 release.
If migrating to MIG v1.73 is not feasible, updated rtl files are required. To obtain these files, please open a Web Case at: http://www.xilinx.com/support/clearexpress/websupport.htm