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AR# 25441

Virtex-5 Embedded Tri-mode Ethernet MAC Wrapper v1.3 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)


This Answer Record contains the Release Notes for the LogiCORE Embedded Tri-mode Ethernet MAC Wrapper v1.3, which was released in the 9.2i IP Update 1 and includes the following:

-General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 25222).


General Information

- Supports automatic generation of HDL wrapper files for the Virtex-5 LXT Tri-Mode Ethernet MAC

- Instantiates user-configurable Ethernet MAC physical interfaces (GMII, MII, RGMII, SGMII and 1000Base-X PCS/PMA configurations are supported)

- Provides a FIFO-based example design

- Provides a demonstration testbench for the selected configuration

New Features

- ISE 9.2i support

- Consolidated the user constraints into a single UCF file to simplify the NGCBuild processing

- Reworked the GMII and RGMII input delays to improve jitter performance. Fixed mode IODELAYs are now instantiated on both the data and clock inputs. Users should specify the values of the delays in the UCF file.

- Updated to latest Virtex-5 GTP attributes.

Bug Fixes

- None

Known Issues

1. For designs using 1000BASE-X or SGMII, the Virtex-5 LXT and SXT ES devices require transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not needed for production devices and are not included in version 1.2 or 1.3 of the core. The previous version of the core, v1.1, did have these registers. Refer to (Xilinx Answer 24166) for more information.

2. When the EMAC wrappers are generated for SGMII with the fabric elastic buffer, Auto Negotiation sometimes does not complete with the current reset logic. The fabric elastic buffer is used by default when the wrappers are generated for Tri-speed operation. For more information and a way to work around this issue, see (Xilinx Answer 29630).

3. When using the Example Design Local Link RX FIFO incorrect data can be read when toggling rd_dst_rdy_n. For more information and a way to work around this issue, see (Xilinx Answer 29660).

AR# 25441
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article