Solution

New Features in v4.1
- ECC support added to Virtex-5 block RAM-based FIFO configurations
- Full range of data count widths now supported for nonsymmetric aspect ratio configurations
- Option to define reset value for full condition flags (FULL, ALMOST_FULL, PROG_FULL). Applies to block RAM, distributed RAM and shift RAM-based FIFO configurations only
- Support added for use of embedded output registers in block RAM FIFO configurations (Virtex-4 and Virtex-5 only)

Bug Fixes in v4.1
- CR 433738: GUI reports incorrect number of built-in FIFOs primitive used
- CR 435835: Programmable Full flag is always asserted even when FIFO is empty as the result of an incorrect threshold setting
- CR 338260: Map errors out with "ERROR:LIT:250 Pins WEA), WEA1, WEA2, WEA# of RAMB16 symbol "physical..." do not share the same signal."
- CR 436886: Write Data Count and Read Data Count overestimate the number of words written or read when core is configured with this combination of options:
.......... First-Word-Fall-Through
.......... Accurate data count using extra logic
.......... Nonsymmetric port aspect ratios
- CR 433637: SBITERR and DBITERR outputs are not driven in behavior
models.
- CR 43392: Maximum programmable empty threshold negate value is
incorrect.
- CR 435874: Programmable full flag behavior is incorrect when the
core is configured with this combination of options:
.......... FWFT
.......... nonsymmetric port aspect ratio
.......... single or multiple programmable full threshold input port.
- CR 443569: Programmable empty flag stuck high when the core is
configured with this combination of options:
.......... block or distributed RAM FIFO
.......... single or multiple programmable empty threshold input port.

General Information
(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator.

Known Issues in v4.1
(Xilinx Answer 29172) In behavioral simulation, power up value for DOUT and VALID signals are undefined
(Xilinx Answer 29173) In VHDL behavioral simulation, DOUT powerup as "x" until the first word falls out
(Xilinx Answer 24003) NCELab issues warnings: "memory index out of declared bounds" in simprims_ver_virtex5_source.v or unisim_ver_virtex5_source.v during Verilog structural and timing simulations in NCSIM for Virtex-5 block RAM FIFOs. The simulation will be successful, and the warnings can be ignored
(Xilinx Answer 23691) Behavioral models are not supported for the built-in FIFO
(Xilinx Answer 20291) Simulation Warning: "*/X_FF RECOVERY Low VIOLATION ON SET WITH RESPECT TO CLK"
(Xilinx Answer 20271) Simulation error on RESET: "Error: /proj/xbuilds/G.36/verilog/src/simprims/X_RAMB16.v(4289): $hold(..."
(Xilinx Answer 29137) "WARNING:Ngdbuild:452 - logical net 'u1/BU2/prog_*_thresh_assert<*>' has no driver" occur during NgdBuild although programmable empty or full is not selected. Warnings can be safely ignored.

Device Issues
Please be aware of Virtex-4 and Virtex-5 Errata posted on
http://www.xilinx.com/support/mysupport.htm
FIFO Generator Core with block Ram configuration is subject to all block RAM issues listed in the errata.

Documentation Changes
- Added clarification on FIFO flag latency.
- Added clarification on actual FIFO depth.

FIFO Generator v3.3 Known Issues
-The FIFO Generator v3.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.3 issues, see (Xilinx Answer 24552).

FIFO Generator v3.2 Known Issues
-The FIFO Generator v3.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.2 issues, see (Xilinx Answer 23847).

FIFO Generator v3.1 Known Issues
-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues
-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 22302).