This Release Note is for the SPI-3 (POS-PHY L3) Physical Layer v5.1 Core released in 9.2i IP Update 1 and contains the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 25222).
New Features in v5.1
- Support added for Virtex-5, Spartan-3A, Spartan-3AN and Spartan-3A DSP device families
- ISE 9.2i support
Bug Fixes in v5.1
- CR428074: Incorrect range on default GUI values for TX_Almost_Full_Assert and TX_Almost_Full_Negate parameters.
- A DCM with a PHASE_SHIFT on its clock is required to meet the OIF specification's 2 ns input timing requirement for Spartan3/3E parts. This solution is only necessary if the system's timing budget cannot permit the PHY core to exceed the 2 ns input requirement. This constraint has been added to the design example provided with the core.
- In the example design, there are some configurations with many channels where the PHY core may fail in MAP or PAR due to either a lack of pins in the example design part or due to an inability to route to speed because of poor pin placement. This problem is due to the fact that the example design runs the backend transfer control pins to I/O, which would not necessarily be done in an actual design.
- In the example design simulation, the demo testbench may send packets to addresses beyond what the user indicated as the maximum number of channels (selected in GUI); this is not a problem because the PHY core will pass any 8-bit address through regardless of the number of channels selected (the number of channels indicates how many channels of flow control information is reported).
- If the following cores do not meet timing with high effort for map and par, users can try running par with the -xe n option.
- In spi3_phy_v5_1 datasheet, Figure7 is incorrect. Please refer to IP lounge for the updated datasheet.