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AR# 25462

LogiCORE RapidIO v4.2 - Release Notes and Known Issues for 9.2i SP3 IP Update 2 (9.2i_IP2)


This Release Note and Known Issues Answer Record is for the RapidIO v4.2 released in 9.2i IP Update 2 and contains the following information:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).


General Information

Starting with v4.1 of the LogiCORE Serial RapidIO solution, the sRIO PHY, RIO Logical IO, and RIO Design Environment Cores have been integrated into a single end-point solution. See (Xilinx Answer 24888) Migrating Serial RapidIO design from v3.1 to v4.1.

New Features in v4.2

- Support added for ISE 9.2i.

Bug Fixed in v4.2

(Xilinx Answer 24837) Stomped packet incorrectly sent after Restart-from-Retry control signal causing protocol error (Packet Not Accepted)

(Xilinx Answer 29263) Receive side buffer design might corrupt packets when many small packets cause the status FIFO to fill

(Xilinx Answer 29233) Repeated, transmitted packet accepted control symbols referencing the same AckID cause loss of AckID sync resulting in duplicated packets and ultimately a port error condition

(Xilinx Answer 24987) CORE Generator fails to generate the core when illegal component names are used

(Xilinx Answer 25318) Design Example provided with the core might not work if you modify "ireq_gnerator.v" file to add other packet transactions

(Xilinx Answer 25319) Using the example design, ireq ports are not connected properly

(Xilinx Answer 25088) For Virtex-4, RX and TX, PLLs might fail to lock or exhibit excess jitter due to incorrect MGT settings

Known Issues in v4.2

(Xilinx Answer 29522) Issues running Synplicity flow

(Xilinx Answer 24967) Select "Engineering Sample" when Targeting ML523 boards Rev A, B or C.

(Xilinx Answer 24968) Logical Layer Receive side does not support stalls on incoming Rx packets; the rx buffer must provide packets to the logical layer without buffer induced stall cycles. The buffer reference design provided with the core is a store and forward buffer and complies with this rule.

(Xilinx Answer 24970) A control symbol which has been scheduled into the transmit pipeline might be lost if reinitialization is force.

(Xilinx Answer 30023) x4 core can train down to x1 using lane 0, but not to other lanes

(Xilinx Answer 30314) Virtex-4, x4 core might intermittently train down to x1 due to MGT lock signal issue.

(Xilinx Answer 30320) Messaging packet has incorrect treq_byte_count

(Xilinx Answer 30054) CAR value incorrect

(Xilinx Answer 29936) Maintenance RESEPONSE packet has incorrect source device ID

(Xilinx Answer 30322) Missing EOF or missing packet on target request interface when sending 8-byte SWRITE

(Xilinx Answer 30323) Re-initialization is not forced following a change to Port Width Override

Known Issues in v4.1

Serial Rapid IO v4.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v4.1, see (Xilinx Answer 23850).

Known Issues in v3.1

Serial Rapid IO v3.1 is now obsolete; you must upgrade to the latest core available through the latest IP Update. For existing known issues in Serial Rapid IO v3.1, see (Xilinx Answer 22319).

AR# 25462
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article