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AR# 25463

LogiCORE Packet Queue v2.2 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

Keywords: CORE Generator, asynchronous, synchronous, common, clocks, memory, asynch, asymmetric, non-symmetric, v2.2

This Release Notes and Known Issues Answer Record is for the Packet Queue v2.2 released in ISE 9.2i IP Update 1 and contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xillinx Answer 25222).

Solution

New Features in v2.2
- Support added for Spartan-3A, Spartan-3AN and Spartan-3A DSP device families
- ISE 9.2i support

Bug Fixes in v2.2
(Xilinx Answer 23709) MAP - "ERROR:LIT:250 - Pins WEA0, WEA1, WEA2, and WEA3 of RAMB16 symbol"

General Information
(Xilinx Answer 22689) Can I automatically flush packets as they are read?
(Xilinx Answer 22681) Core stops responding when writing large packets
(Xilinx Answer 22682) Flushing the packet being read causes data corruption
(Xilinx Answer 22685) Flushing too many packets causes data corruption

Known Issues in v2.2
- If the following cores do not meet timing with high effort for MAP and PAR, users can try running PAR with the "-xe n" option.
- In Packet Queue, if the WR_DST_DSC and RD_SRC_DSC input signals are not tied, they will be driven to a constant logic '0' by the core.

Packet Queue v2.1 Known Issues
Packet Queue v2.1 is now obsolete. Please upgrade to the latest version of the core.
For information on Packet Queue v2.1 existing issues, see (Xilinx Answer 24562).

Packet Queue v1.2 Known Issues
Packet Queue v1.2 is now obsolete. Please upgrade to the latest version of the core.
For information on Packet Queue v1.2 existing issues, see (Xilinx Answer 22842).
AR# 25463
Date Created 09/04/2007
Last Updated 03/03/2009
Status Active
Type General Article