Added software support for ISE 9.2i.
- CR 437252: VHDL module dependencies on std_logic_arith and std_logic_unsigned should be removed
- CR 439167: VHDL downto statements appear in Verilog example source module
- CR 439316: Latest guidelines for RX termination settings should be reflected in the Wizard
- The example design out of the GTP wizard v1.6 that is generated for Synplify (Vendor set to Synplicity in the project settings) could error out in NGDBuild with the following error:
"ERROR:LIT:241 - Attribute PCS_COM_CFG on GTP_DUAL instance "rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i" has a hexadecimal value, "0001011010000000101000001110", which is too large. PCS_COM_CFG should contain a maximum of 28 bits."
To work around this issue, PCS_COM_CFG needs to be set in the UCF.
To do this, type the following line in the UCF for each GTP_DUAL instance:
INST <path to GTP instance>/gtp_dual_i PCS_COM_CFG=28'h1680a0e;
The value in the UCF will overwrite the value in the EDF, and the design will go through NGDBuild. XST does not have this problem.
- If you set the comma alignment smaller than the datapath width, incoming data can be aligned to multiple positions. The example design does not account for this and might indicate errors even though data is being received correctly.
- In the case of Clock correction, the GTP wrapper in the Example design is configured correctly, but the block RAM data does not have embedded Clock-correction characters.
- In ES silicon, the logic was added to make TX timing more reliable. Timing closure at fabric rates of 312.5 MHz and higher might require significant effort. For best results, use a 16- or 20-bit interface for line rates higher than 1.25 Gb/s.
- RX buffer bypass in Oversampling mode is not supported.