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AR# 25484

LogiCORE XAUI v7.2 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)


This Answer Record contains the Release Notes for the LogiCORE XAUI v7.2 Core, which was released in 9.2i IP Update 1, and includes the following:

- New Features

- Bug Fixes

- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 25222).


New Features

- Support added for ISE 9.2i

- Updated Virtex-4 RocketIO Wrappers with changes from RocketIO Wizard 1.5

- Updated Virtex-5 RocketIO Wrappers with changes from RocketIO GTP Wizard 1.6

- New attribute PCS_COM_CFG on GTP_DUAL

- PMA_COM_CFG removed from UCF - This is now the default in ISE 9.2i sp1

- Renamed rocketio_init_tx to tx_sync for Virtex-5 to be consistent with the Virtex-5 RocketIO GTP Wizard

- Updated tx_sync with changes from Virtex-5 RocketIO GTP Wizard 1.6

- Selected family, package, and speed grade are now propagated into UCF constraint file and SCR script file

Bug Fixes

- XAUI VHDL example design has undriven signal, that causes Synplify to trim gt11 init blocks (CR 436549)

The Virtex-4 block-level module would always declare a soft_reset signal

that would be undriven when using a configuration vector. This was because

Synplify tied this to "1," causing a permanent reset. The soft_reset signal

is now declared only when using MDIO.

- Register added to input config_vector[2..3] (CR 432938)

This input to the core is now registered internally to fix a potential

timing problem.

- IUS timing simulation used MIN sdf delay instead of MAX sdf delay (CR 439540)

The IUS timing simulation script used a MIN sdf delay which was

inconsistent with the Modelsim script that used MAX sdf delay. Both

scripts now use MAX sdf delay.

- MGT Rx signals not registered between Virtex-4 MGT and channel bonding monitor logic (CR 438622)

The Virtex-4 block-level used unregistered MGT outputs as inputs to the

channel bonding monitor logic. This made timing closure difficult in some

circumstances. This has been rewired to use the registered MGT outputs

that were already present.

- Virtex-5 Verilog : TXENPMAPHASEALIGN not connected to tx init block (CR 442039)

The Virtex-5 Verilog block-level did not properly connect the

TXENPMAPHASEALIGN port between the tx init block and the GTP wrapper.

Known Issues

1. Virtex-4 Example design timing simulation fails with error "Transmit fail: data mismatch at XAUI serial interface." For more information, see (Xilinx Answer 24678).

2. Virtex-5 Example design timing simulation fails with error "Testbench timed out." Or 'X' seen of TX serial output of GTP. For more information, see (Xilinx Answer 24677).

3. Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down in order to meet timing. These were included in v7.0 of the XAUI core but have not been included in v7.1 or v7.2 as they are not needed for production devices. If Virtex-5 ES silicon must be targeted, the wrapper file for the GTP can be regenerated with the RocketIO wizard. Refer to (Xilinx Answer 24168) for instructions on how to generate the file.

4. Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not effect XST. For more information, see (Xilinx Answer 25469).

5. Virtex-5 GTP channel bonding is sometimes not successful after a cable pull/replug or disconnect/reconnect with the link device. This can be recovered from by resetting the entire XAUI core or the RXRESET on the MGTs. The next version of the XAUI core due out in 10.1 will add code to monitor channel bonding and issue the reset when this condition occurs.

AR# 25484
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article