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AR# 25485

VCS SmartModel, SWIFT Interface - How do I use the MGT and PPC SmartModels in VCS for ISE 9.1x (and later) and Linux Enterprise edition?

Description

The Hard IP simulation flow uses Synopsys VMC models to simulate the IBM PowerPC microprocessor and RocketIO multi-gigabit transceiver. Since VMC models are simulator-independent models derived from the actual design, they are accurate evaluation models. To simulate these models, you must use a simulator that supports the SWIFT interface.

How are these models used in VCS in Linux Enterprise edition?

Solution

For running SmartModel with 64-bit VCS, refer to (Xilinx Answer 24798).

Run compxlib to precompile libraries when running VHDL simulation.

Information on compxlib can be found in the software manuals at:

http://www.xilinx.com/support/documentation/dt_ise.htm

Setup File

The setup file is a description of variables that must be set for correct simulation.

Example

setenv Xilinx <Xilinx path>

setenv VCS_HOME <VCS path>

setenv LM_LICENSE_FILE <license.dat>:${LM_LICENSE_FILE}

setenv VCS_SWIFT_NOTES 1

setenv LMC_HOME $Xilinx/smartmodel/lin/installed_lin

setenv LMC_CONFIG $LMC_HOME/data/linux.lmc

setenv VCS_CC gcc

setenv LD_LIBRARY_PATH $LMC_HOME/sim/pli/src:$LMC_HOME/lib/linux.lib:$LD_LIBRARY_PATH

setenv PATH ${LMC_HOME}/bin:${VCS_HOME}/bin:${PATH}

setenv PATH ${Xilinx}/bin/lin:${PATH}

Change the parameters in "< >" to match your system configuration.

Simulate File

The simulate file is an example VCS compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.

Example

vcs -lmc-swift +neg_tchk \

<design>.v <testbench>.v \

${Xilinx}/verilog/src/glbl.v \

-y ${Xilinx}/verilog/src/unisims +libext+.v \

-y ${Xilinx}/verilog/src/simprims +libext+.v \

-y ${Xilinx}/smartmodel/lin/wrappers/vcsmxverilog +libext+.v \

sim -l vcs.log

Change the parameters in "< >" to match your design files and testbench.

NOTE: Virtex-5 SmartModels have negative setup and hold times. VCS_MX requires the use of +neg_tchk for negative timing checks to be enabled.

AR# 25485
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article