This Answer Record contains the Release Notes for the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII v9.0 Core, which was released in 9.2i IP Update 1. It includes the following:
- New Features
- Bug Fixes
- Known Issues
For installation instructions and design tools requirements, see (Xilinx Answer 25222).
- Support added for ISE 9.2i.
- Ten-Bit Interface (TBI) configurations enhanced to support the SGMII standard.
- SGMII configurations include the option to generate without Auto-Negotiation or MDIO management.
- Virtex-4 and Virtex-5 devices: reworked the GMII and TBI input delays to improve jitter performance. Fixed mode IODELAYs are now instantiated on both the data and clock inputs. Users should specify the values of the delays in the UCF file.
- Updated to latest Virtex-5 GTP attributes.
- Virtex-5 LXT ES silicon requires transmit signals between the fabric and GTP to be registered and locked down to meet timing. These registers are not included in version 8.1 or v9.0 of the core, but if LXT ES silicon is being used, the previous version of the core v8.0 did have these registers; refer to (Xilinx Answer 24165) for more information.
- Virtex-5 Timing simulation might fail with transmit data mismatch. For more information, see (Xilinx Answer 24729).
- The core fails to generate all files when using the SGMII standard with the TBI from within the ISE Project Navigator GUI. To work around this, the core can be successfully generated when CORE Generator is run as a standalone tool. The standalone core can then be added to your ISE project.
- Virtex-4 GT11 init blocks can have glitching if not encoded as one-hot in Synplify. This issue does not effect XST. For more information, see (Xilinx Answer 25469).