UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 25487

LogiCORE Gigabit Ethernet MAC v8.3 - Release Notes and Known Issues for 9.2i IP Update 1 (9.2i_IP1)

Description

This Answer Record contains the Release Notes for the LogiCORE Gigabit Ethernet MAC v8.3 Core, which was released in 9.2i IP Update 1. It includes the following:  

 

- New Features 

- Bug Fixes  

- Known Issues 

 

For installation instructions and design tools requirements, see (Xilinx Answer 25222).

Solution

New Features 

 

- Support added for ISE 9.2i. 

 

- Virtex-4 and Virtex-5 devices: reworked the GMII and RGMII input delays to improve jitter performance. Fixed mode IODELAYs are now instantiated on both the data and clock inputs. Users should specify the values of the delays in the UCF file. 

 

Bug Fixes  

 

- None. 

 

Known Issues 

 

- When using the Example Design Local Link RX FIFO, incorrect data can be read when toggling rd_dst_rdy_n. For more information and a way to work around this issue, see (Xilinx Answer 29660).

AR# 25487
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article