General InformationLicense Requirements As of the ISE 9.1i sp2 IP Update 1 release, the LogiCORE Endpoint Block Plus for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license, visit the product lounge at:
http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?iLanguageID=1&sGlobalNavPick=&sSecondaryNavPick=&key=V5_PCI_Express_Block_Plus ES Silicon Please refer to
(Xilinx Answer 24697) for information on targeting Virtex-5 engineering samples (ES) silicon with this core.
New Features- Added VHDL simulation support for VCS and NC-Sim.
- Changed design hierarchy to allow for future family expansion.
Bug Fixes- CR 440287: Selecting a Maximum Payload Size of 128 bytes causes the implementation to fail at NGDBuild
- CR 442180: Certain data flows might cause received packets to be lost when using Continuous Request. Added additional GUI options to alleviate lost packets
- CR 440848: VHDL test bench creates incorrect clock frequency
Known Issues- Refer to the "pcie_blk_plus_release_notes.txt" file delivered with the core for known issues at the time of the release.
- Some x1, x4, and x8 designs might not meet timing with the default MAP and PAR settings. In order to obtain timing closure, designers might be required to use multiple PAR seeds or floorplanning. Using Multi-Pass Place and Route (MPPR), designers can try multiple cost tables in order to meet timing. For more information on using MPPR, see the Development System Reference Guide in the Software Manuals found at:
http://www.xilinx.com/support/library.htm.
Designers might also have to floorplan and add advanced placement constraints for both their design and the core to meet timing.
-To further assist in meeting timing, use the "-xe c" (extra effort level = continuous) for both MAP and PAR. By default this option is included for PAR in the provided implementation scripts. Adding this to MAP will improve the tools ability to meet timing.
- Core Receive Flow Control Credit Available signals are unavailable; trn_rfc_{p,np}h_av[7:0] and trn_rfc_{p,np}d_av[11:0] are not indicating correct values. These signals are considered informational only and are not critical for correct operation of the Endpoint application.
- When generating a core, CORE Generator will display "WARNING:coreutil - coreutil:39 - Parsing of check license val <> failed." This warning can be safely ignored. The core will still be generated.
- See
(Xilinx Answer 24174) if you receive an error stating "ERROR:coreutil - Failure to generate output products" in CORE Generator.
- See
(Xilinx Answer 25427) for known issues found in the Virtex-5 Built-in Block for PCI Express that are fixed in the Endpoint Block Plus Wrapper.
- Packets implementing Phantom Functions are not properly passed to the user application. If the function number field is anything other than 000, the TLP is discarded by the Block Plus Endpoint wrapper. A solution to this problem is under investigation.
- See
(Xilinx Answer 29294) regarding excessive simulation times.
- See
(Xilinx Answer 29287) to download a critical patch for the v1.4 Block Plus Wrapper. This patch fixes problems regarding the "Advanced Flow Control Options" in the CORE Generator GUI.