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AR# 25494

LogiCORE Endpoint Block for PCI Express v1.5 - Release Notes and Known Issues for 9.2i IP Update 1


This Release Note and Known Issues Answer Record is for the LogiCORE Endpoint Block for PCI Express v1.5 released in 9.2i IP Update 1. It contains the following:

- General Information

- New Features

- Bug Fixes

- Known Issues

For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 25222).


General Information

As of 9.1i sp 2 IP Update 1 Release, the LogiCORE Endpoint Block for PCI Express requires a license to generate and implement the core. There is no charge for this license. To obtain the license, visit the product lounge at:


New Features

- Created an additional PCIE_INTERNAL_1_1 output pin (LLKTXCONFIGREADYN) on PCIE_EP to work around a potential issue where the PCIe core receives a MsgD packet with 2DW payload. This pin was formerly a test pin.

- Created an additional GTP_DUAL_TEST attribute (PCS_COM_CFG) on GTP_DUAL UNISIM model. When PLL_DIVSEL_FB value is 1, changing this attribute to 28'h1680A07 improves the performance of the block.

Bug Fixes

- CR 433878: The "slot clock configuration" checkbox keeps getting set in GUI even if previously unchecked when any other parameter is changed.

- CR 438765: Use of logical inequalities instead of case inequalities in pcie_tasks.v. Using logical inequalities allows checking for presence of X in the buffer.

- CR 440898: Design fails PTC when user_clk is 125MHz or 62.5MHz.

Known Issues

- Refer to the "endpoint_block_for_pcie_express_release_notes.txt" file delivered with the core for known issues at the time of the release.

- Example Design: No split transactions. Completer cannot break a read request into two or more separate completions.

- Example Design: Can only process packets in VC0 and only on traffic class 0.

- Example Design: Endpoint does not initiate traffic without further modifications to the code.

- Some 250 MHz designs may not meet timing. Introducing area constraints and maxdelay constraints in the ucf may help the design to meet timing.

- - See (Xilinx Answer 25473) for known issues found in the Virtex-5 Built-in Block for PCI Express that are fixed in the Endpoint Block Plus Wrapper. Users of the Endpoint Block Wrapper will need to work around these issues.

AR# 25494
Date 12/15/2012
Status Active
Type General Article
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