This Release Note and Known Issues Answer Record is for the LogiCORE Initiator/Target v3.163 for PCI released in 9.2i IP Update 1, and contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 25222).
The LogiCORE PCI v3.163 supports only Virtex-4, Spartan-3, and older architectures. For Virtex-5 devices, use the v4.2 PCI Core. For more information on this core, refer to (Xilinx Answer 25496).
When migrating from CORE Generator 8.1i to 9.1i IP Update 1 and later, new licenses are required for the LogiCORE Initiator/Target v3.161 and later for PCI. For more information, see (Xilinx Answer 24718).
- See (Xilinx Answer 22921) for general information regarding timing closure in Virtex-4 devices.
- Support for ISE 9.2i Service Pack 2
- XC3S400A device support
- XC3SD1800A and XC3SD3400A support
-CR 438149: S_CYCLE64 and OE_ADO_T64 signals went undefined in simulation due to
conflicting assignments in the master cfg.v/vhd file.
-CR 441111: Fixed Synplify error: "@E: CD358 :"<core_path>/example_design/pci_lc.vhd":557:2:557:10 No architecture is available for entity <component_name>"
- Refer to the release notes text file, "pci64_release_notes.txt," delivered with the core for known issues at the time of the release.
- CR 433036: In rare situations, PAR might report that it has successfully routed a design but TRCE might still report hold-time violations. This peculiar discrepancy has been observed in Virtex-4 PCI 64/66 designs.
This is a known PAR issue that is scheduled to be fixed in ISE 10.1i. In the meantime, users can work around this problem by over constraining any offending net with a slightly negative hold time. For example, if the failing net is IRDY_N, add the following to the UCF file:
NET "PCI_CORE/IRDY_IO" TNM = PADS:PCI_PADS_X;
TIMEGRP "PCI_PADS_X" OFFSET = IN 3 VALID 2.97 BEFORE "PCLK" TIMEGRP "ALL_FFS";
TIMEGRP "PCI_PADS_X" OFFSET = OUT 6 AFTER "PCLK" TIMEGRP "ALL_FFS";
This constrains IRDY_N to a hold time of -30 ps, a number that seems to work well.
- See (Xilinx Answer 25217) regarding duplicated PCI core entries in the CORE Generator taxonomy list.
- With some core configurations, the run_xilinx.sh and run_xilinx.bat might contain the wrong path to the UCF file. The problem occurs on some Spartan and older Virtex architectures when generating a 33 MHz core. The NGDBUILD command will point to the DIRT directory as:
ngdbuild -sd ../../src/xpci -sd ../synthesis -uc ../../src/DIRT/<ucf file name> pcim_top
Replace "DIRT" with "ucf"
ngdbuild -sd ../../src/xpci -sd ../synthesis -uc ../../src/ucf/<ucf file name> pcim_top