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AR# 25500

9.2i IP Update 1 CORE Generator IP-DSP - What's New and Known Issues List

Description

Keywords: ISE, LogiCORE, Binary Counter, Comparator, Direct Digital Synthesis, DDC, Distributed Arithmetic FIR Filter, FIR Compiler, MAC FIR, MACC FIR, Multiplier Generator, DVB S2 FEC Encoder, FFT, Floating-point, Divider Generator, Pipelined Divider, RAM Based Shift Register, TCC Decoder 3GPP, CTC Encoder 802.16e, LDPC Encoder 802.16, Viterbi

This Answer Record for the CORE Generator contains the IP-DSP What's New and Known Issues addressed in the 9.2i IP Update 1, and contains the following:

- New Features
- Bug Fixes
- Known Issues

For installation instructions and design tools requirements, see (Xilinx Answer 25222).

Solution

What's New in 9.2i IP Update 1

3GPP Downlink Chip Rate v1.0
Features in v1.0
- The 3GPP Downlink Chip Rate Core provides an optimized core designed to support 3GPP TS Release 6 for Femto-cell, Pico-cell and Macro-cell solutions.
- Supports Virtex-4, Virtex-5 and Spartan-3A DSP devices.

3GPP RACH v1.0
Features in v1.0
- The 3GPP RACH Preamble Detector core provides a Release 6 Compliant, optimized core for Femto-cell and Pico-cell solutions.
- Available for Virtex-4, Virtex-5 and Spartan-3A DSP.

3GPP Searcher v1.0
Features in v1.0
- The 3GPP Searcher core is a highly integrated solution for identifying the multiple transmission paths of users in a 3GPP uplink. The core includes all the logic required for scramble code generation, correlation, accumulation and filtering in a single co-processor, easily integrated with a DSP or microprocessor.
- Supports Virtex-4, Virtex-5 and Spartan-3A DSP devices.

LogiCORE FIR Compiler v3.1
New Features in v3.1
- ISE 9.2i software support.
- Rounding of output sample values, with Non-Symmetric, Symmetric and Convergent options.
- Limiting of bit growth based on actual coefficient values (reduces resource utilization).

Bug Fixes in v3.1
- CR 435181: PQ Decimation does not work correctly with multi-column implementation structure.
- CR 435182: Incorrect output when core is configured with this combination of options: Interpolate symmetry with rate of 10, odd number of taps, and fully parallel configuration.
- CR 437327: Output data may glitch during reloadable coefficient switch-over.
- CR 437779: Out of memory error when trying to generate a filter with 25-bit coefficients.
- CR 438019: Issue with PQ Interpolation single channel configuration: Input data is not latched and must be held.
- CR 439042: Cannot generate core with half-band symmetry.


Known Issues in 9.2i IP Update 1

3GPP Downlink Chip Rate v1.0
- None.

3GPP RACH v1.0
- None.

3GPP Searcher v1.0
- None.

LogiCORE FIR Compiler v3.1
- FIR Complier Known Issues. See (Xilinx Answer 29138).


Known Issues in Existing IP

LogiCORE CIC v3.0
- The CIC Filter v3.0 exhibits overflow for inputs that use the complete dynamic bit range of the data input. See (Xilinx Answer 12480).
- The CIC Filter v3.0 reset. See (Xilinx Answer 20187).
- The CIC Filter v3.0 input and output date format. See (Xilinx Answer 17210).

LogiCORE Complex Multiplier v2.1
- Spartan-3E support for the Complex Multiplier. See (Xilinx Answer 21467).

LogiCORE CORDIC v3.0
- Output does not change when the output width is larger than 12 bits. See (Xilinx Answer 20371).
- LogiCORE CORDIC v3.0 - Why does the behavioral simulation for the CORDIC square root mode require four extra clocks after asserting the ND signal before the data will be processed? See (Xilinx Answer 23934).

LogiCORE Digital Down Convertor (DDC)
- Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters. See (Xilinx Answer 5366).
- In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format. See (Xilinx Answer 14202).

LogiCORE DDS Compiler v1.1
- Why is the behavioral simulation output incorrect when using the structural simulation model? See (Xilinx Answer 24316).
- Why are the outputs on the DDS CORE Generator GUI always displayed as 32-bits wide? See (Xilinx Answer 24410).
- Why are the outputs on the DDS schematic symbol always displayed as 32-bits wide? See (Xilinx Answer 24412).

LogiCORE 1024-pt FFTv1.0
- The block RAM configurations in the FFT/IFFT data sheet do not match the hardware configurations. See (Xilinx Answer 15311).

LogiCORE 16-pt FFT v2.0
- The slice utilization of a 16-point Virtex FFT is greater than that of a 64-point FFT. See (Xilinx Answer 8765).

LogiCORE 256-pt FFT v2.0
- The FFT for a Virtex-II device causes PAR warnings and errors. See (Xilinx Answer 13173).

LogiCORE 32-pt FFT v1.0
- A Verilog model is not available for the FFT Core. See (Xilinx Answer 11155).

LogiCORE 64-pt FFT v2.0
- The RESULT signal is not reset properly in the 64-point FFT v2.0. See (Xilinx Answer 15383).

LogiCORE FFT
- Simulation of all fixed netlist FFT (64, 256, 1024) Cores generates many warnings. See (Xilinx Answer 14861).
- Information on output connections to the fixed netlist FFT (64, 256, 1024) Cores during a write operation to RAM X (TMS configuration). See (Xilinx Answer 9288).

LogiCORE Fast Fourier Transform (xFFT) v4.1 / rev1
- Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris? See (Xilinx Answer 24317).
- Why does the Fast Fourier Transform Core take so long to generate? See (Xilinx Answer 24318).
- Why is the multiplier usage always zero when targeting Virtex-II/-II Pro, Spartan-3/E/A? See (Xilinx Answer 24437).
- Why are my results incorrect when I use the Radix-2 Lite implementation, with the block floating point option? See (Xilinx Answer 24463).
- Why do I see a degradation in the signal to noise ratio of the slot test, near the edges of the transform? See (Xilinx Answer 29237)
- Why are the output results of the Pipelined Streaming IO xFFT architecture not symmetrical? Or why do I see differences between the Radix 2 Minimum Resource implementation and the Pipelined Streaming IO FFT implementation? See (Xilinx Answer 23247).

- Large FFT point size generation times. See (Xilinx Answer 21988).
- Some bitwidths fail to allow core to implement. See (Xilinx Answer 20307).
- First frame after multi-cycle reset might be incorrectly marked as valid. See (Xilinx Answer 24436).


LogiCORE Floating-Point Operators v3.0
- Why do I not see a resource estimation graph for my Floating Point operator function? See (Xilinx Answer 24039).
- Why do FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when I attempt to customize them on Solaris? See (Xilinx Answer 24317).

LogiCORE MAC v4.0
- Virtex-4 maximum number of cycles. See (Xilinx Answer 21511).
- When I set up my Multiply Accumulate v4.0 Core to have a wide input (e.g., 24x16) and use an output that is less than full precision, why is there no activity on the output of my core during simulation? See (Xilinx Answer 24096).

LogiCORE Multiplier Generator v10.0
- Why does my Virtex-5 LUT-based multiplier give incorrect output results in post-MAP simulation, post-PAR simulation, and hardware when I do not use any pipelining? See (Xilinx Answer 23705).
- How do I dynamically control the sign of my A port input, or why can I no longer use the a_signed input to control the sign of my A data input? See (Xilinx Answer 23599).
- Why can I not add handshaking signals to my multiplier? See (Xilinx Answer 23598).
- How do I generate a multiplier with an asynchronous clear? See (Xilinx Answer 23600).

LogiCORE Pipelined Divider v3.0
- How to do I perform a Verilog behavioral simulation? See (Xilinx Answer 20615).

LogiCORE RAM-based Shift Register v9.0
- Large RAM-based Shift Registers fail to generate. See (Xilinx Answer 21410).
- Why is the LogiCORE RAM-based Shift Register v9.0 almost 10 times larger than the LogiCORE RAM-based Shift Register v8.0, when targeting Virtex or Spartan-II? See (Xilinx Answer 23696).

LogiCORE Turbo Product Code Encoder and Decoder (TPC)
- How can I get the TPC to compile using XST, without incurring MAP Pack error: "ERROR:Pack:679"? See (Xilinx Answer 22258).
- Why does the reset need to be applied for the code to be changed? See (Xilinx Answer 24298).
- Why does the OutputRDY signal Remain high for six clock cycles after the output FIFO is empty? See (Xilinx Answer 24299).
AR# 25500
Date Created 09/04/2007
Last Updated 03/30/2009
Status Archive
Type General Article