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AR# 25508

Virtex-5 IODELAY - What does the SIGNAL_PATTERN attribute do?

Description

Keywords: Virtex-5, Chipsync, IODELAY, SIGNAL, PATTERN, FPGA, EDITOR, MODE, SETUP, HOLD

I see an attribute called 'SIGNAL_PATTERN' on the IODELAY module, and it appears to default to DATA in the 9.2.2 and newer design tools versions. What does this attribute do?

Solution

This is a new attribute that was added to help determine if the IODELAY is being used on a clock or data pattern. As we state in the Virtex 5 Data sheet, there will be jitter added if the IODELAY is used with a Data Pattern. There is no jitter added when it is used on a clock path. The Timing Tools will automatically add in jitter to the required set up and hold times if the SIGNAL_PATTERN is set to 'DATA'.

To set this attribute to clock:

Verilog:

defparam IDELAY_inst.SIGNAL_PATTERN ="CLOCK";

VHDL

attribute SIGNAL_PATTERN of IDELAY_inst : label is "CLOCK";

AR# 25508
Date Created 09/04/2007
Last Updated 02/11/2008
Status Archive
Type General Article