NCSIM, SmartModel/SWIFT Interface - How do I use the MGT and PPC 64-bit SmartModels with NCSIM?
Description
The Hard IP simulation flow uses Synopsys VMC models to simulate the IBM PowerPC microprocessor and the RocketIO multi-gigabit transceiver. Since VMC models are simulator-independent models derived from the actual design, they are accurate evaluation models. To simulate these models, you must use a simulator that supports the SWIFT interface.
Starting with ISE 9.1i, Xilinx has 64-bit SmartModel Support.
How are these models used in NCSIM?
Solution
Xilinx recommends using 32-bit simulation unless a 64-bit simulation is needed because of memory space limitation. Simulation performance tends to be slower in a 64-bit simulator.
For 32-bit simulation, please refer to (Xilinx Answer 25517).
Running the simulation with Cadence NC-Verilog - Linux
Several files in the "$Xilinx/smartmodel/lin64/simulation/ncverilog" directory can help you set up and run a simulation utilizing the SWIFT interface. A description of each file follows:
setup file - A description of variables that must be set for correct simulation.
For example:
setenv Xilinx <Xilinx path>
setenv CDS_INST_DIR <Cadence path>
setenv LM_LICENSE_FILE <license.dat>:$LM_LICENSE_FILE
setenv LMC_HOME $Xilinx/smartmodel/lin/installed_lin
setenv LMC_CONFIG $LMC_HOME/data/amd64.lmc
setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LMC_HOME/sim/pli/src:$LMC_HOME/lib/amd64.lib:$LD_LIBRARY_PATH
setenv LMC_CDS_VCONFIG $CDS_INST_DIR/tools/verilog/bin/vconfig
setenv PATH ${LMC_HOME}/bin ${CDS_INST_DIR}/tools/bin ${PATH}
setenv PATH ${Xilinx}/bin/lin64 ${PATH}
You are responsible for changing the parameters included within "< >" to match your system configuration.
simulate file - An example NC-Verilog compilation simulation script that illustrates which files must be compiled and loaded for simulation. You can modify this file to simulate a design by including the design and testbench files appropriately.
For example:
ncverilog +nc64bit\
<design>.v <testbench>.v \
${Xilinx}/verilog/src/glbl.v \
-y ${Xilinx}/verilog/src/unisims +libext+.v \
-y ${Xilinx}/verilog/src/simprims +libext+.v \
-y ${Xilinx}/smartmodel/lin/wrappers/ncverilog +libext+.v \
+loadpli1=swiftpli:swift_boot +incdir+$LMC_HOME/sim/pli/src \
+access+r+w
NCVHDL Setup:
Running the simulation with Cadence NC-VHDL - Linux
Several files in the "$Xilinx/smartmodel/lin64/simulation/ncvhdl" directory can help you set up and run a simulation utilizing the SWIFT interface. A description of each file follows:
setup file - A description of variables that must be set for correct simulation.
For example:
setenv Xilinx <Xilinx path>
setenv CDS_INST_DIR <Cadence path>
setenv LM_LICENSE_FILE <license.dat>:$LM_LICENSE_FILE
setenv LMC_HOME $Xilinx/smartmodel/lin/installed_lin
setenv LMC_CONFIG $LMC_HOME/data/amd64.lmc
setenv LD_LIBRARY_PATH $CDS_INST_DIR/tools/lib:$LMC_HOME/sim/pli/src:$LMC_HOME/lib/amd64.lib:$LD_LIBRARY_PATH
setenv LMC_TIMEUNIT -12
setenv PATH ${LMC_HOME}/bin ${CDS_INST_DIR}/tools/bin ${PATH}
setenv PATH ${Xilinx}/bin/lin64 ${PATH}