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AR# 2558

4.1i SIMPRIMS - CLB flip-flops and latches may have zero setup delay in an SDF netlist for a routed design. (VHDL, Verilog)


Keywords: zero, setup, hold, SDF, Verilog, VHDL, flip-flop, register, latch, NGD2VER, NGD2VHDL

Urgency: Standard

General Description:
Some of my flip-flops or latches appear to have zero setup times in an SDF delay file. Why does this happen?


Zero setup delay is commonly seen in the SDF file SETUP records for flip-flops and latches in M1.

For example:

(WIDTH (posedge CLK) (2000:2000:2000))
(WIDTH (negedge CLK) (2000:2000:2000))
(SETUP IN (posedge CLK) (0:0:0))

These zero SETUP delays occur because the delay distribution algorithm in the M1 back-annotation tool has annotated 0 setup/hold times on flip-flops and latches; instead, it has annotated non-zero delay values to gates and carry logic. This is not be a source of concern because the timing, when viewed at the external pins of the CLB (the only place our speed files guarantee it), is correct.

On the other hand, CLB flip-flops or latches with NO setup records in the SDF will usually correspond to registers that have been disabled (i.e., registers whose output is always a constant value due to their clocks being disabled and their INIT values matching either VCC or GND on their data inputs, etc.). Such registers will still appear in the netlist, but will have no timing attributes whatsoever.


- It is also possible for flip-flops to have setup requirements from the data input with respect to the clock, but to not have setup requirements from the CE or SET/RST inputs to the clock if the CE and local SET/RST functions are not used on a given instance of the flip-flop.

- If the local SR signal is used, it will have a SETUP (recovery) constraint.

- A global reset (e.g., GSR) will not have a setup requirement or SDF setup record.
AR# 2558
Date Created 08/31/2007
Last Updated 08/25/2003
Status Archive