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AR# 2586

14.x Timing/Constraints, Virtex-4 and newer and Spartan-3 and newer - How to handle PLL/DCM/MMCM Timing Constraints

Description


What known issues are associated with constraining paths of the DLL/DCM taps? Also, how does Timing Analyzer handle constraints and the various taps of the DLL/DCM/PLL?

Note: See (Xilinx Answer 6905) for more information on these issues. There are also similar taps on the DCM as the DLL.

Solution


CLKDLL Documentation
For more information on the CLKDLL implementation, refer to the following documents:
- (Xilinx XAPP132): "Using the Virtex Delay-Locked Loop"
- Libraries Guide

Timing Constraints
The CLKDLL provides many powerful features that aid in high-speed digital designs. In addition to these features, the Xilinx tool set can perform timing-based place and route. The timing tools use timing constraints: PERIOD, OFFSET, and FROM:TO constraints. These are discussed in detail in this Answer Record.

Figure 1 contains one implementation of the CLKDLL:
Figure 1 - One CLKDLL Implementation with Onesy and Two Time as Outputs
Figure 1 - One CLKDLL Implementation with Onesy and Two Time as Outputs


PERIOD
You can apply a PERIOD constraint to the DLL using the following methods, as illustrated in Figure 2:
1. Using the pad net name method (preferred):

NET "PADCLKIN" TNM_NET = "PADCLKIN";
TIMESPEC TS_PADCLKIN = PERIOD "PADCLKIN" 30 ns;

2. Using the DLL output net name method:

NET "ZERO" PERIOD = 30 ns;
or
NET "ZERO" TNM_NET = "ZERO";
TIMESPEC TS_ZERO = PERIOD "ZERO" 30 ns;

Figure 2 - Another CLKDLL Implementation with Zero and Ninety as Outputs
Figure 2 - Another CLKDLL Implementation with Zero and Ninety as Outputs


Xilinx recommends using the pad net name method in which you use a TIMESPEC. If the input to a DLL is constrained using this method, NGDBuild writes out constraints for the output clocks of the DLL. These constraints are related to the input clock with respect to frequency and phase. Since these clocks are related to the input clock, then cross-clock domain analysis is automatically performed by the Timing Analyzer.

Example
The following example illustrates using the DLL CLK2x output and putting a TIMESPEC constraint on the input of the DLL:

Clock constraint for the input of the DLL in the UCF file:
NET "PADCLKIN" TNM_NET = "PADCLKIN";
TIMESPEC "TS_PADCLKIN" = PERIOD "PADCLKIN" 20 ns HIGH 50 %;

Constraints created by NGDBuild for the DLL output:
TS_clk2x = PERIOD TIMEGRP "clk2x" TS_PADCLKIN / 2.000000 HIGH 50.000 % ;

Example
The following example illustrates using the DLL CLKDV output and putting a TIMESPEC constraint on the input of the DLL:

Clock constraint for the input of the DLL in the UCF file:
NET "PADCLKIN" TNM_NET = "PADCLKIN";
TIMESPEC "TS_PADCLKIN" = PERIOD "PADCLKIN" 20 ns HIGH 50 %;

Constraints created by NGDBuild for the DLL output:
TS_clkdv = PERIOD TIMEGRP "clkdv" TS_PADCLKIN * 2.500000 HIGH 50.000 % ;

The CLKDLL provides duty cycle correction on all 1x clock outputs so that all 1x outputs, by default, have a 50/50 duty cycle. The DUTY_CYCLE_CORRECTION property (TRUE by default) controls this feature. (Remember this when creating PERIOD constraints based on the DLL outputs.) It is strongly recommended to always set the DUTY_CYCLE_CORRECTION attribute to TRUE. Setting this attribute to FALSE does not necessarily produce output clocks with the same duty cycle as the source clock.

Example
The following is an example of the change in duty cycle:

Original Constraint: NET "ZERO" PERIOD = 30 ns HIGH 7 ns;
Modified Constraint: NET "ZERO" PERIOD = 30 ns HIGH 15 ns;

The modified constraint accounts for the duty cycle correction. Duty cycle correction also occurs on the 2x and DV outputs. This correction cannot be controlled by the property.

NOTE: For more details on PERIODs through CLKDLLs, see (Xilinx Answer 6905).

PAD-to-SETUP (OFFSET IN BEFORE)
When you create pad-to-setup requirements, make sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET IN constraint. (For the following example, refer to the schematic in Figure 3.) If your register is clocked by the net from the CLK90 pin of the DLL, which has a PERIOD of 20 ns, the OFFSET value should be adjusted by an additional 5 ns.

Original Constraint: NET "PAD_IN" OFFSET = IN 10 BEFORE "PADCLKIN";
Modified Constraint: NET "PAD_IN" OFFSET = IN 15 BEFORE "PADCLKIN";

NOTE: The clock net name required for OFFSET constraints is the clock net name attached to the IPAD. In this case, it is "PADCLKIN", not "CLK90". Refer to Figure 2 for the CLK network.

Figure 3 - Schematic Layout for OFFSET IN & OFFSET OUT Constraints
Figure 3 - Schematic Layout for OFFSET IN & OFFSET OUT Constraints


CLOCK to PAD (OFFSET OUT AFTER)
When you create clock-to-pad requirements, be sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET OUT constraint. (For the following example, please refer to the schematic in Figure 3.) If your register is clocked by the net from the CLK90 pin of the DLL, which has a PERIOD of 20 ns, the OFFSET value should be adjusted by 5 ns less than the original constraint.

Original Constraint: NET "PAD_OUT" OFFSET = OUT 15 AFTER "PADCLKIN";
Modified Constraint: NET "PAD_OUT" OFFSET = OUT 10 AFTER "PADCLKIN";

FROM:TO In Multiple Clock Domains
When using PERIOD constraints, you must properly constrain the paths between multiple clock domains. Refer to Figure 4 for an example of a path that runs between clock domains.

Figure 4 - Schematic of a Data Path between Clock Domains
Figure 4 - Schematic of a Data Path between Clock Domains


If a PERIOD constraint is applied to the CLK90 and CLK0 output pins of the DLL, the CLK0 PERIOD constraint will constrain the paths between flip-flops A and B. This type of constraining can lead to setup violations, as illustrated in the waveforms of Figure 5.

After the phase shift between CLK90 and CLK0, the path from A to B has 25% less time than the PERIOD constraint allows. To properly constrain these paths, use a FROM:TO constraint.

Figure 5 - Waveform illustration of CLKIN, CLK0, and CLK90
Figure 5 - Waveform illustration of CLKIN, CLK0, and CLK90


Example FROM:TO Constraint:

NET "CLK90" TNM_NET = "CLK90";
NET "CLK0" TNM_NET = "CLK0";
TIMESPEC "TS_CLK90_2_CLK0" = FROM "CLK90" TO "CLK0" 15ns;

The TIMESPEC is set at 15 ns because the PERIOD on CLK0 is 20 ns.

This type of correction is required for all clock domain interactions with the different phases of clocks. The following table contains some of the possible configurations and associated corrections:

CLKDLL..............................................Required Correction
CLK0 to CLK90...................................Subtract 75%
CLK0 to CLK180.................................Subtract 50%
CLK0 to CLK270.................................Subtract 25%
CLK270 to CLK0.................................Subtract 75%
CLK270 to CLK90...............................Subtract 50%
CLK270 to CLK180.............................Subtract 25%

For more details on PLL/DCM interactions with timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/itp/xilinx10/books/docs/timing_constraints_ug/timing_constraints_ug.pdf

Constraints Editor
The Constraints Editor handles constraints that are specific to the CLKDLL as follows:

PERIOD
The Constraint Editor creates PERIOD constraints based on the DLL input name method; this is set in the Global tab.

PAD-to-SETUP and CLOCK-to-PAD
When creating pad- or register-specific OFFSET constraints in the Constraints Editor, you must specify the clock pad net name for flip-flops driven by the CLKDLL. In Figure 2, "PADCLKIN" is the pad net name used in OFFSET constraints; this is set in the Ports tab.

FROM:TO
Groups can be created based on the DLL outputs and used to create time specifications that control multiple clock domain paths; this is set in the Advance tab.
AR# 2586
Date Created 08/21/2007
Last Updated 11/14/2012
Status Active
Type Known Issues
Tools
  • ISE Design Suite - 12
  • ISE Design Suite - 13
  • ISE Design Suite - 14