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AR# 2703

3.1i NGD2VER/NGD2VHDL - How do I create HDL simulation files using Alliance software for FPGAs?

Description

Keywords: SDF, Verilog, VHDL, HDL, Alliance

Urgency: Standard

General Description:
How do I create HDL simulation files using Alliance Software for FPGAs?

Solution

Simulation files can be created at four stages of the FPGA implementation flow:

Behavioral (Synthesis only)
Post-NGDBuild
Post-Map Timing
Post Route Timing

Simulation Stages

Behavioral Simulation:

Behavioral simulation files are generated using tools from your behavioral simulator. In most cases, you can read the Verilog and VHDL files directly into the simulator.

Functional Simulation:

Functional simulation is a gate-level simulation with unit delays. For HDL designs, functional simulation can be used to verify your design's synthesis. For schematic designs, functional simulation can be used to verify the correct behavior of your design. For designs that mix HDL components and schematic components, functional simulation can be used to verify the integration and the overall functionality.

If you instantiate LogiBLOX components in your design, make sure to generate simulation netlists.

Command Line:

To generate functional simulation files, use the following command line sequence:

1. ngdbuild <design top-level netlist> -p <part>
2. ngd2ver <design>.ngd -w <output netlist name>.v
or
ngd2edif <design>.ngd -w <output netlist name>.edn
or
ngd2vhdl <design>.ngd -w <output netlist name>.vhd
or
ngd2xnf <design>.ngd -w <output netlist name>.xnf

Top-level netlists can be EDIF, XNF, or SXNF formats.

NOTE: You can use the -help <family> option to see how to automatically create testbench templates. For example,

ngd2ver -help xc4000ex

Graphical Interface:

Functional simulation files cannot be directly generated through the graphical tools. To create functional simulation files:

1. In the Design Manager, identify the version you want to simulate.

2. Copy the following file to a simulation directory and rename it as <design>.ngd

<design directory>/xproj/<version>/<family>.ngd

3. Run the command line sequence above.


Post-Map Simulation:

Post-Map simulation is a gate-level simulation with real delays for the gates and estimated delays for the routing. This simulation is useful in determining whether there are obvious timing issues in your design, without having to spend time completing place and route.

If you have already completed a functional simulation of your design, you can more easily determine whether there are obvious timing issues by examining the summary in the post-map timing report (Logic Level Timing Report in the Report Browser). If the post-map timing report reveals timing issues, you can examine specific paths more closely by running the Timing Analyzer on your <map>.ncd file.

Command Line:

To create post-map simulation files, use the following command line sequence:

1. ngdanno <mapped>.ncd <mapped>.ngm
2. ngd2ver <design>.nga -w <output netlist name>.v
or
ngd2edif <design>.nga -w <output netlist name>.edn
or
ngd2vhdl <design>.nga -w <output netlist name>.vhd
or
ngd2xnf <design>.nga -w <output netlist name>.xnf

NGD2VER will automatically embed the timing information in an <output netlist name>.sdf file.

NOTE: You can use the -help <family> option to see how to automatically create testbench templates. For example,

ngd2ver -help xc4000ex

Graphical Interface:

Post-map timing simulation files cannot be directly generated through the graphical tools. To create post-map timing simulation files:

1. In the Design Manager, identify the revision you want to simulate.
2. Copy the following file to a simulation directory and rename it as <design>.ncd

<design directory>/xproj/<version>/<revision>/map.ncd

3. Run the command line sequence above.


Post-Route Timing Simulation:

Post-Route simulation is a gate-level simulation with real delays for the gates and real delays for the routing. This simulation stage is also useful in verifying that there are no design specification problems, timing issues, or design implementation problems. Bugs are much easier to trace in timing simulation than by using a logic analyzer.

If you have already completed a functional simulation of your design, you also determine whether there are timing issues by examining the summary in the post-route timing report (Post-Layout Timing Report in the Report Browser). If the post-route timing report reveals some timing issues, you can examine specific paths more closely by running the Timing Analyzer on your <design>.ncd file.

Command Line:

To create post-map simulation files, use the following command line sequence:

1. ngdanno <placed_and_routed>.ncd <mapped>.ngm
2. ngd2ver <design>.nga -w <output netlist name>.v
or
ngd2edif <design>.nga -w <output netlist name>.edn
or
ngd2vhdl <design>.nga -w <output netlist name>.vhd
or
ngd2xnf <design>.nga -w <output netlist name>.xnf

NOTE: You can use the -help <family> option to see how to automatically create testbench templates. For example,

ngd2ver -help xc4000ex

NGD2VER will automatically embed the timing information in an <output netlist name>.sdf file.

Graphical Interface:

Post-route simulation files can be directly generated through the graphical tools. To create post-route timing simulation files:

1. In the Options dialog, select "Produce Timing Simulation Data". You can access the Options dialog from the Flow Engine menu by selecting Setup->Options.

2. In the Options dialog, select the Edit Template button for the Implementation Template. In the Implementation Template dialog, select the Interface tab.

3. Select the simulation netlist format: EDIF, VHDL, VERILOG, or XNF. If you select EDIF, use the Vendor switch to select whether you want to create Viewlogic, Mentor Graphics, or a generic version of EDIF.

4. Select the "Correlate Data to Input Design" button if you want all of your original design signals in your timing simulation netlist. Because your design was optimized during the implementation process, some of the signals and symbols in your original netlist have been optimized out. Selecting the "Correlate Data" option causes the tools to insert optimized names into your timing simulation netlist so you can use your functional simulation testbench to stimulate your timing simulation netlist.

If you use MAP -oe or -os command line options, or if you set Optimization Strategy = Balance, Speed or Area in the Implementation Template, the Correlate Data option will not be able to insert all of the optimized names back into the timing simulation netlist.

5. If you select the Verilog or VHDL netlist format, you can select the Always Create Power On Reset Port button. This will create a port for the global reset signal and connect it to the global reset wire. If this option is not selected, the global reset wire will still exist in the timing simulation netlist.

6. In order to create the simulation files, the Timing step in the Flow Engine must be run. After the Timing step finishes processing, your timing simulation files will be in your design directory. They will be called:

time_sim.<extension>
(<extension> = xnf, edn, v, vhdl)
AR# 2703
Date Created 08/31/2007
Last Updated 11/13/2002
Status Archive
Type ??????