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AR# 29014

9.1i SP3 Virtex-5 DRC - "ERROR:PhysDesignRules:1407 - Dangling pins on block:<IODELAY_inst/IODELAY_inst>:<IODELAY_IODELAY>. For DELAY_SRC programming I or IO the IDATAIN input pin of IODELAY must be connected."

Description

Keywords: BitGen, DRC, IODELAY, DELAY_SRC

When I run a design with a IODEALY primitive instantiated in HDL code and this design does not instantiate IBUF primitive, the following error message occurs:

"ERROR:PhysDesignRules:1407 - Dangling pins on block:<IODELAY_inst/IODELAY_inst>:<IODELAY_IODELAY>. For DELAY_SRC programming I or IO the IDATAIN input pin of IODELAY must be connected."

IODELAY primitive is instantiated as below:
IODELAY_inst : IODELAY
generic map (
DELAY_SRC => "I", -- Specify which input port to be used
-- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN
IDELAY_TYPE => "VARIABLE", -- "DEFAULT", "FIXED" or "VARIABLE"
IDELAY_VALUE => 0, -- 0 to 63 tap values
ODELAY_VALUE => 0, -- 0 to 63 tap values
REFCLK_FREQUENCY => 200.0) -- Frequency used for IDELAYCTRL
-- 175.0 to 225.0
port map (
DATAOUT => qdr_q_int1, -- 1-bit delayed data output
C => cal_clk, -- 1-bit clock input
CE => q_dly_ce, -- 1-bit clock enable input
DATAIN => qdr_q_int, -- 1-bit internal data input
IDATAIN => '0', -- 1-bit input data input (connect to port)
INC => q_dly_inc, -- 1-bit increment/decrement input
ODATAIN => '0', -- 1-bit output data input
RST => q_dly_rst, -- 1-bit active high, synch reset input
T => '1' -- 1-bit 3-state control input
);

Solution

To resolve this issue, the port DATAIN cannot be used. IDATAIN port of IODELAY primitive should be used. The IODELAY primitive is instantiated as below:

IODELAY_inst : IODELAY
generic map (
DELAY_SRC => "I", -- Specify which input port to be used
-- "I"=IDATAIN, "O"=ODATAIN, "DATAIN"=DATAIN
IDELAY_TYPE => "VARIABLE", -- "DEFAULT", "FIXED" or "VARIABLE"
IDELAY_VALUE => 0, -- 0 to 63 tap values
ODELAY_VALUE => 0, -- 0 to 63 tap values
REFCLK_FREQUENCY => 200.0) -- Frequency used for IDELAYCTRL
-- 175.0 to 225.0
port map (
DATAOUT => qdr_q_int1, -- 1-bit delayed data output
C => cal_clk, -- 1-bit clock input
CE => q_dly_ce, -- 1-bit clock enable input
DATAIN => '0', -- 1-bit internal data input
IDATAIN => qdr_q_int, -- 1-bit input data input (connect to port)
INC => q_dly_inc, -- 1-bit increment/decrement input
ODATAIN => '0', -- 1-bit output data input
RST => q_dly_rst, -- 1-bit active high, synch reset input
T => '1' -- 1-bit 3-state control input
);
AR# 29014
Date Created 01/24/2008
Last Updated 06/05/2008
Status Active
Type General Article