UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29019

Schematic - "DesignEntry:218 Net is connected to source pins and/or I/O markers, but not connected to any load pin or I/O marker"

Description

When I implement or synthesize a schematic design, the following message occurs:

"DesignEntry:218 Net <net_name> is connected to source pins and/or I/O markers, but not connected to any load pin or I/O marker"

Solution

This is a valid error, and it occurs when a net is connected to a source (output pin of a symbol or an input I/O marker) and is not connected to a load (Input pin of a symbol or an output I/O marker).

To remove this message, connect the net to the appropriate I/O marker or load pin.

To change this error to a warning message, follow these steps:

1. Select Edit -> Preferences -> Schematic Editor -> Check.

2. Change the value of "Consider Loadless Nets and IO as" to Warning.

AR# 29019
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article