UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29045

LogiCORE FIR Compiler v3.0 – Why does the FIR Compiler appear to hang when the Synchronous Clear (SCLR) option is not selected and targeting a Virtex-II/-II Pro or Spartan-3/-A/-AN device?

Description

Why does the FIR Compiler appear to hang when the Synchronous Clear (SCLR) option is not selected and targeting a Virtex-II/-II Pro or Spartan-3/-A/-AN device?

Solution

This issue is fixed in the FIR Compiler v3.1. 

 

Not selecting the SCLR is not allowed for the Spartan-3 non-DSP family parts; the core must have a RESET pin. Unfortunately, the GUI in the FIR Compiler v3.0 does not restrict you from making this selection, which can cause the netlister to hang and not finish. Consequently, you must make sure that the SCLR control option is selected. 

 

See (Xilinx Answer 29138) for a detailed list of LogiCORE FIR Compiler Release Notes and Known Issues.

AR# 29045
Date Created 10/28/2007
Last Updated 05/22/2014
Status Archive
Type General Article