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AR# 29051

LogiCORE Fast Fourier Transform (FFT) v3.1 - Why does the Verilog simulation model output not match the timing shown in the FFT data sheet?

Description

When simulating the Verilog behavioral simulation model of the FFT v3.1 core, the xn_index and xk_index count output should change on every clk cycle, according to the data sheet. When I keep the START signal high, the xn_index and xk_index count with a frequency six times lower than that of clk. 

 

Why is this happening?

Solution

This issue is fixed in the FFT v4.1. 

 

This is a known problem and the way to work around this is to use the VHDL simulation model. 

 

Please See (Xilinx Answer 29209) for a detailed list of LogiCORE Fast Fourier Transform (FFT) Release Notes and Known Issues.

AR# 29051
Date Created 10/28/2007
Last Updated 05/22/2014
Status Archive
Type General Article