UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29108

9.1 Timing/Spartan3ADSP - Rising to Rising PERIOD Path from DSP48 component is not analyzed

Description

When I run a timing analysis on my design with a DSP48 component, the analysis for rising to rising path with the DSP as the source is only half the period and it fails timing.

When will this be fixed?

Solution

The DSP48A?s timing model was using Negedge instead of Posedge. This issue is fixed in ISE 9.2

AR# 29108
Date Created 10/28/2007
Last Updated 01/18/2010
Status Archive
Type General Article