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AR# 29127

MIG v2.3, 3.0 - A parsing error occurs when attempting to "Update Design" on PPC440 user project

Description

When updating a MIG DDR2 PPC440 "user_design" project, the following errors occur, and might include a crash of "mig.exe": 

 

"Parsing Error 

Parsing error in file 

C:/Xilinx/10.1/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v2_3/bin/nt/../../data/fpga_tlb/virtex5/fx/_tlib.xml 

 

File Open Error 

Unable to open 

C:/Xilinx/10.1/ISE/coregen/ip/xilinx/other/com/xilinx/ip/mig_v2_3/bin/nt/../../data/dlib/virtex5/ddr2_sdram/ppc_ucfs/ddr2_72__xc5vfx70t-ff665_banks_.ucf" 

 

How do I resolve this issue and update a PPC440 MIG design?

Solution

The MIG GUI currently does not support the updating of a "user_design" .prj file. To work around the issue, either use the "example_design" .prj file, or modify the "user_design" .prj to change: 

 

<PPC440>1</PPC440> 

to: 

 

<PPC440>0</PPC440> 

 

For more information on the "Update Design" process, see (Xilinx Answer 29313) - "MIG v2.0, v2.1, v2.2, v2.3 - When changing a MIG-generated Virtex-5 DDR2 SDRAM pin-out, both the UCF and top-level HDL parameters MUST be updated".

AR# 29127
Date Created 10/02/2008
Last Updated 05/20/2014
Status Archive
Type General Article