Virtex-4 Datasheet (DS302 (v2.1) March 27, 2007) has PPC Max Frequency ('CPMC405CLOCK frequency' in Table15) as 350MHz for -10, 400MHz for -11, and 450MHz for -12 device.
Does the PowerPC Max Frequency, "CPMC405CLOCK frequenc,"' include the DCM jitter?
Yes, it includes the DCM jitter. The Maximum PowerPC Clock frequency has been specified in the data sheet based on the following configuration:
It uses two cascaded DCMs to generate the core clock for speedbinning. CLKFX output of the first one was fed into the second one and CLK 2X of the second one was used to feed the core.
Also note that the CPU clock uses the CLK FX, which has the worse Jitter value. The jitter value is available through the architecture Wizard for a given M (Multiply) and D (Divide) values.
As an example, if a user wants to use an external oscillator with 100ps jitter and with one DCM feed, CLK0 to PPC, he can use the following formula to calculate the possible max PPC clock frequency.
1/([CPMC405CLOCK minimum pulse width, High] + [CPMC405CLOCK minimum pulse width, Low] + 100ps)
For Virtex-4FX-10 devices,
1/(1.43ns + 1.43ns + 100ps) = 337.8MHz
Note: Please refer to (Xilinx Answer 18181) for the rules for cascading two DCMs in series.