UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29138

LogiCORE IP Finite Impulse Response Compiler (FIR Compiler) - Release Notes and Known Issues

Description

This Answer Record contains the Release Notes and Known Issues list for the CORE Generator software LogiCORE IP FIR Compiler.

The following information is listed for each version of the core:
  • New Features
  • Bug Fixes
  • Known Issues

LogiCORE IP FIR Compiler Lounge:
http://www.xilinx.com/products/ipcenter/FIR_Compiler.htm

Note: The FIR Compiler has superseded all previously released Xilinx FIR cores, including the Distributed Arithmetic FIR and the MAC FIR.

Solution

LogiCORE IP FIR Compiler General Issues
  • Software Support for the Virtex-6 FPGA Lower Power parts was added in this release, but this IP is not yet supported and cannot be generated from the CORE Generator software. To work around this issue, you can set your project to target an equivalent Virtex-6 LXT device which allows you to generate a place holder IP that can be regenerated when support for the Virtex-6 Lower Power parts is added in 11.3.
  • Long generation time: The core can take a long time to generate when specified with a large number of coefficient sets, approximately 100. The number of coefficients per set and specification of computers used also influences the generation time.
  • (Xilinx Answer 5366) Information for converting from floating-point to fixed-point coefficients for Xilinx DA FIR and MAC FIR filters.
  • I cannot use the multi-column support when my coefficients are symmetrical.

 

LogiCORE IP FIR Compiler v6.3 Initial Release in ISE Design Suite 13.3. Supported Devices (ISE)

  • All Series 7 devices
  • All Virtex-6 Devices
  • All Spartan-6 Devices
Supported Devices (Vivado)
  • All Series 7 devices
New Features
  • Ongoing new device support.
  • Advanced Interleaved Channels (Configurable Bandwidth support)
  • Multi-column support for symmetric filter implementations
  • Re-introduction of Hilbert Transform, Single Rate Half-Band and Interpolated filters
  • C Model
Bug Fixes
  • FIR Compiler v6.x - GUI may crash when Maximize_Dynamic_Range is selected
  • FIR Compiler v6.x - Reload port allows Boolean type in System Generator
  • (Xilinx Answer 40200) FIR Compiler v6.x - Latency information in the GUI doesn't match the core
  • (Xilinx Answer 40769) FIR Compiler v6.x - Multi-column filters will not map/place
  • (Xilinx Answer 41707) FIR Compiler v6.2 - The output for a Fractional Rate is in bursts rather than at regular intervals
  • (Xilinx Answer 42305) FIR Compiler v6.x - Event I/F mismatches between model and core
  • (Xilinx Answer 42727) FIR Compiler v6.2 - Multi-Channel core data comes out on the wrong channel. The output shift channels when using a multi-channel, interpolate by 2, odd number of symmetrical coefficients, with an oversample rate of 3 with Block RAM selected for memory implementation
Known Issues (ISE)
  • Unsupported v5.0 features - The following features are not supported by v6.3:
    • Distributed Arithmetic
    • Polyphase filter bank
  • Memory collision errors - Netlist or UniSim structural model simulation may report Block RAM memory collision errors. These errors are issued by the Block RAM primitive when a write occurs and the read and write addresses match. However, a read or write event is qualified by read enable or write enable respectively.
    In operation, read and write events never occur to the same address at the same time so functionality is not affected by these apparent collisions
Known Issues (Vivado)
  • Unsupported v5.0 features - The following features are not supported by v6.3:
    • Distributed Arithmetic
    • Polyphase filter bank
  • (Xilinx Answer 52201) Why do I get an Application Error when trying to synthesize using 2012.2 Vivado Synthesis?

 

LogiCORE IP FIR Compiler v6.2

There is a v6.2 Rev2 patch available in (Xilinx Answer 42260). This patch is intended to fix issue listed below as (Xilinx Answer 42305) and (Xilinx Answer 42727).

Initial Release in ISE Design Suite 13.1.

Supported Devices

  • Virtex-7 XT/-1L
  • Kintex-7 -1L
  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
New Features
  • ISE 13.1 software support
  • Includes Transpose Architecture with AXI4-Stream interface.
  • Optional S_AXIS_DATA FIFO
    • Input FIFO enables burst data transfer but requires additional resources.
  • Optional data vector reset
    • Select if ARESETn resets the control signals and the data vector or the control signals only. Data vector reset requires additional resources.
Bug Fixes
  • CR 582524 Polyphase decimation, symmetry, single channel, 1 tap per phase output mismatch
  • CR 581746 Fractional decimation, single channel BRAM data memory output error
  • CR 582443 Error in RFD control logic results in filter being inactive for one clock cycle longer than expected
Known Issues
  • Unsupported v5.0 features - The following features are not supported by v6.1:
    • Distributed Arithmetic and Transpose Multiply Accumulate architectures.
    • Half-band coefficient optimization for Single Rate filters. Note: This optimization is still available for rate change filters.
    • Hilbert Transform.
    • Interpolated filter.
    • Polyphase filter bank.
  • Memory collision errors - Netlist or UniSim structural model simulation might report block RAM memory collision errors. These errors are issued by the block RAM primitive when a write occurs, and the read and write addresses match. However, a read or write event is qualified by read enable or write enable respectively. In operation, read and write events never occur to the same address at the same time, so functionality is not affected by these apparent collisions.
  • (Xilinx Answer 40200) Why does my core simulation not match the latency value in the CORE Generator interface?
  • (Xilinx Answer 40769) Why does my multi-column FIR Compiler implementation fail to route?
  • (Xilinx Answer 41707) Why is the output for a Fractional Rate in bursts, rather than at regular intervals?
  • (Xilinx Answer 42305) Why do I see errors on the event interface, for my multi-channel FIR, even when the data is properly aligned?
  • (Xilinx Answer 42727) Why does the output shift channels when using a multi-channel, interpolate by 2, odd number of symmetrical coefficients, with oversample rate of 3 with Block RAM selected for memory FIR Compiler implementation?
  • (Xilinx Answer 43299) Why does a symmetrical interpolation filter use more DSP slices when the coefficients are >=18 bits in Spartan-6?
  • (Xilinx Answer 41591) How to line up input data with the correct channel
  • (Xilinx Answer47352) (IDS 13.1) Why do I get an error when attempting to open the FIR Compiler GUI?

LogiCORE IP FIR Compiler v6.1

Initial Release in ISE Design Suite 12.4.

Supported Devices

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
New Features
  • ISE 12.4 software support
  • Re-introduction of Fixed Fractional rate change type
Bug Fixes
  • All FIR Compiler v6.0 Known Issues
Known Issues
  • Unsupported v5.0 features - The following features are not supported by v6.1:
    • Distributed Arithmetic and Transpose Multiply Accumulate architectures.
    • Half-band coefficient optimization for Single Rate filters. Note: This optimization is still available for rate change filters.
    • Hilbert Transform.
    • Interpolated filter.
    • Polyphase filter bank.
  • Memory collision errors - Netlist or UniSim structural model simulation might report block RAM memory collision errors. These errors are issued by the block RAM primitive when a write occurs and the read and write addresses match. However, a read or write event is qualified by read enable or write enable respectively. In operation, read and write events never occur to the same address at the same time, so functionality is not affected by these apparent collisions.
  • (Xilinx Answer 40200) Why does my core simulation not match the Latency value in the CORE Generator interface?
  • (Xilinx Answer 40769) Why does my multi-column FIR Compiler implementation fail to route?
  • (Xilinx Answer 41707) Why is the output for a Fractional Rate in bursts, rather than at regular intervals?
  • (Xilinx Answer 42727) Why does the output shift channels when using a multi-channel, interpolate by 2, odd number of symmetrical coefficients, with oversample rate of 3 with Block RAM selected for memory FIR Compiler implementation?
  • (Xilinx Answer 43299) Why does a symmetrical interpolation filter use more DSP slices when the coefficients are >=18 bits in Spartan-6?
  • (Xilinx Answer 41591) How to line up input data with the correct channel

LogiCORE IP FIR Compiler v6.0
Initial Release in ISE Design Suite 12.3.

Supported Devices

  • Virtex-6 XC CXT/LXT/SXT/HXT
  • Virtex-6 XQ LXT/SXT
  • Virtex-6 -1L XC LXT/SXT
  • Spartan-6 XC LX/LXT
  • Spartan-6 XA
  • Spartan-6 XQ LX/LXT
  • Spartan-6 -1L XC LX
New Features
  • ISE 12.3 software support
  • AXI4-Stream Interfaces
  • ARESETn (active low synchronous clear) resets both data and control
Bug Fixes
    N/A
Known Issues
  • Distributed Arithmetic and Transpose Multiply Accumulate architectures
    • Fixed Fractional rate change type.
    • Half-band coefficient optimization for Single Rate filters. Note: This optimization is still available for rate change filters.
    • Hilbert Transform.
    • Interpolated filter.
    • Polyphase filter bank.
  • Memory collision errors - Netlist or UniSim structural model simulation might report block RAM memory collision errors. These errors are issued by the block RAM primitive when a write occurs and the read and write addresses match. However, a read or write event is qualified by read enable or write enable respectively. In operation, read and write events never occur to the same address at the same time, so functionality is not affected by these apparent collisions.
  • (Xilinx Answer 40200) Why does my core simulation not match the Latency value in the CORE Generator interface?
  • (Xilinx Answer 40769) Why does my multi-column FIR Compiler implementation fail to route?
  • (Xilinx Answer 41707) Why is the output for a Fractional Rate in bursts, rather than at regular intervals?
  • (Xilinx Answer 43299) Why does a symmetrical interpolation filter use more DSP slices when the coefficients are >=18 bits in Spartan-6?
  • (Xilinx Answer 41591) How to line up input data with the correct channel

LogiCORE IP FIR Compiler v5.0
Initial Release in ISE Design Suite 11.2.

New Features

  • ISE 11.2 software support
  • Virtex-6 and Spartan-6 support added
  • Leverages the pre-adder in Virtex-6 and Spartan-6 XtremeDSP Slice for symmetric filter implementation
  • Extended clock and sample frequency range for Fixed Fractional Rate Decimation structure
  • Capability added to specify filter coefficients as a vector directly in the GUI
  • Capability added to specify hardware over-sampling specification as a sample period
  • Supports automatic core update from FIR Compiler v4.0 and FIR Compiler v3.2
Bug Fixes
  • CR 489883 Incorrect output from behavioral model
    - (Xilinx Answer 32068) Why do I see incorrect outputs when performing a behavioral simulations of a semi-parallel filter?
  • CR 498427 Incorrect behavior from "Generate chan_in value in advance" parameter
    - (Xilinx Answer 31996) When the "Generate chan_in value in advance" parameter is used, why is the chan_in output delayed by the specified number of cycles, rather than being output early by the specified number of cycles?
  • CR 499955, 499956 Half-band decimation or interpolate by 2 3-tap filters incorrectly inferred
    - (Xilinx Answer 31989) Why doesn't my decimate or interpolate by 2 3 tap half-band filter work in post-PAR simulation, or in hardware?
Known Issues
  • (Xilinx Answer 32943) Why does the FIR Compiler coefficient width require 1 extra bit, when the initial load of Integer Only coefficients is greater than the default width of 16?
  • (Xilinx Answer 32947) Why is the GUI so slow, when changing the coefficient vector field?
  • (Xilinx Answer 32945) When selecting a Distributed Arithmetic FIR implementation, why do I see mismatches between the behavioral and post implementation simulation?
  • (Xilinx Answer 35786) Why does the reloadable DA FIR architecture fail to generate with a RAMB16 error when targeting Spartan-6 devices?
  • (Xilinx Answer 40620) Why is the FIR Compiler v5.0 larger than the FIR Compiler v4.0
  • (Xilinx Answer 43299) Why does a symmetrical interpolation filter use more DSP slices when the coefficients are >=18 bits in Spartan-6?

LogiCORE IP FIR Compiler v4.0 rev1
Initial Release in ISE Design Suite 10.1 IP Update 3.

New Features

  • Same as v4.0
Bug Fixes
  • (Xilinx Answer 31841) Why does the FIR Compiler fail to generate with an out-of-memory error for a filter that generated without any problems in FIR Compiler v3.2?
  • (Xilinx Answer 32068) Why do I see incorrect outputs when performing behavioral simulations of a semi-parallel filter?
Known Issues
  • Same as v4.0
LogiCORE IP FIR Compiler v4.0
Initial Release in ISE Design Suite 10.1 IP Update 2.

New Features

  • Poly-phase filter bank structure for Channelizer applications
  • Extended Data and Coefficient Width range
  • Transpose Multiply-Accumulate architecture
  • Parallel data path support
  • Behavioral model
  • Additional control port options
Bug Fixes
  • CR453335: SCLR and CE - When SCLR and CE have been selected, CE must be asserted for SCLR to operate correctly. This has been corrected so that SCLR can be asserted without CE.
  • CR467427: Distributed Arithmetic architecture resource utilization greater than DA FIR v9.0 Core.
Known Issues
  • (Xilinx Answer 31535) Why does the FIR Compiler have more fractional bits than actual bits for my Coefficient set?
  • (Xilinx Answer 31717) What are the limitations that should be considered when selecting the taps for a Spartan-3A DSP device due to the broken DSP48A cascades?
  • (Xilinx Answer 31841) Why does the FIR Compiler fail to generate with an out of memory error for a filter that generated without any problems in FIR Compiler v3.2?
  • (Xilinx Answer 31989) Why doesn't my decimate or interpolate by 2 3-tap half-band filter work in post-PAR simulation, or in hardware?
  • (Xilinx Answer 31996) When the "Generate chan_in value in advance" parameter is used, why is the chan_in output delayed by the specified number of cycles, rather than being output early by the specified number of cycles?
  • (Xilinx Answer 32068) Why do I see incorrect outputs when performing a behavioral simulations of a semi-parallel filter?
  • (Xilinx Answer 32300) Why does the FIR Compiler fail to generate core if the total number coefficients is more than 34816?
  • (Xilinx Answer 32344) How to access the reload order information, when using the FIR Compiler v4.0 in System Generator for DSP?
  • (Xilinx Answer 34149) When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioral and post-par simulation results, when targeting a Spartan-3A DSP?

LogiCORE IP FIR Compiler v3.2
Initial Release in ISE Design Suite 9.2i IP Update 2.

New Features

  • Full feature support for the following families: Virtex-II, Virtex-II Pro, Spartan-3, Spartan-3E, and Spartan-3A.
Bug Fixes
  • CR447610 Coefficient Reload - The switch-over to the newly reloaded coefficient set can result in corruption of the output samples for some single rate half-band filters.
  • CR447610 Unable to place generated filter - It is not possible to place the generated core when Output Rounding is enabled increasing the total number of DSP48s being utilized to three.
Known Issues
  • (Xilinx Answer 29774) The data sheet does not mention that the CE has precedence over SCLR
  • (Xilinx Answer 29744) Why does the CORE Generator "View Resource Utilization (Under Original Project Settings)" results differ from a ISE MAP report?
  • (Xilinx Answer 30621) Why do I see an extra bit on the COEF_DIN input port of my reloadable interpolation filter, when the *_reload.txt file does not contain any additions for subtractions?

LogiCORE IP FIR Compiler v3.1
Initial Release in ISE Design Suite 9.2i IP Update 1.

New Features

  • ISE 9.2i software support
  • Rounding of output sample values, with Non-Symmetric, Symmetric and Convergent options
  • Limiting of bit growth based on actual coefficient values (reduces resource utilization)
Bug Fixes
  • CR 435181: PQ Decimation does not work correctly with multi-column implementation structure
  • CR 435182: Incorrect output when core is configured with this combination of options: Interpolate symmetry with rate of 10, odd number of taps, and fully parallel configuration
  • CR 437327: Output data might glitch during reloadable coefficient switch-over
  • CR 437779: Out of memory error when trying to generate a filter with 25-bit coefficients
  • CR 438019: Issue with PQ Interpolation single channel configuration - Input data is not latched and must be held
  • CR 439042: Cannot generate core with half-band symmetry
Known Issues
  • (Xilinx Answer 29423) Why does the FIR Compiler fail when trying to use a COE file that used to work with the MAC FIR or Distributed Arithmetic FIR?
  • (Xilinx Answer 29424) Why does the GUI seem to freeze if I have a large number of coefficients in my COE file?
  • (Xilinx Answer 29566) Why do I receive an error stating that I need a larger part, even though I know I have enough DSP48s in the target part?
  • (Xilinx Answer 29575) Why do I see a glitch on the output of my reloadable single rate half-band filter when switching coefficient sets?
  • (Xilinx Answer 29239) Why do I receive the following error: "Wrong Coefficient Name: coefficient_width, the Radix name and the coefficients names should be one of: radix coefdata" when I use a COE file generated from the FDATool in MATLAB?
  • (Xilinx Answer 29048) Why does the core generation process hang when generating a fractional rate filter for a Virtex-II/-II Pro or Spartan-3/-3A/-3AN device?

LogiCORE IP FIR Compiler v3.0 rev1
Initial Release in ISE Design Suite 9.1i IP Update 2.

New Features

  • Spartan-3A DSP support
Bug Fixes
  • Same as v3.0
Known Issues
  • Same as v3.0

 

LogiCORE IP FIR Compiler v3.0
Initial Release in ISE Design Suite 9.1i IP Update 1.

New Features

  • Support added for ISE 9.1i software
  • Maximum number of channels increased to 64
  • Maximum number of coefficient sets increased to 256
  • Supports reloading of multiple coefficient sets
  • Maximum integer rate change increased to 64
  • Fractional rate changes up to 64/63 now supported
  • Exploits symmetry when interpolating by an even rate with an odd number of coefficients, reducing resource utilization
Bug Fixes
  • CR 424680: Failure to generate a decimating half-band filter
  • CR 426435: Inter-column pipeline uses SRL16s
  • CR 435508: GUI causes error in batch mode due to obsolete check
Known Issues
  • (Xilinx Answer 14202) In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.
  • (Xilinx Answer 24317) Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris?
  • (Xilinx Answer 29423) Why does the FIR Compiler fail, when trying to use a COE file that used to work with the MAC FIR or Distributed Arithmetic FIR?
  • (Xilinx Answer 29424) Why does the GUI seem to freeze if I have a large number of coefficients in my COE file?
  • (Xilinx Answer 29566) Why do I receive an error stating that I need a larger part, even though I know I have enough DSP48s in my target part?
  • (Xilinx Answer 29568) Why do I see a glitch on the output of my non-symmetric interpolating multi-channel filter, when switching coefficient sets?
  • (Xilinx Answer 29569) Why does my filter miss input data, when I have an over-sampled, single channel, factional rate change filter?
  • (Xilinx Answer 29571) Why is my filter output incorrect when I have a factional rate change filter that spans multiple DSP48 columns?
  • (Xilinx Answer 29572) Why is the output of my symmetrical interpolate by 10 filter incorrect when using the full-parallel implementation with an odd number of coefficients?
  • (Xilinx Answer 29573) Why are the results of my interpolating half-band filter incorrect when I using the optimize for speed option?
  • (Xilinx Answer 29574) Why do I see incorrect outputs after resetting my single multiply accumulate (MACC) engine half-band filter when the data is stored in Block Memory?
  • (Xilinx Answer 29577) Why does my single-rate, single channel, full-parallel, non-symmetrical filter with coefficients greater than 18 bits fail to generate when targeting Virtex-5?
Distributed Arithmetic Filter Architecture: Multiply Accumulator Filter Architecture for all devices other than Virtex-4 and Virtex-5:
  • (Xilinx Answer 22706) Why does my single-rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"?
  • (Xilinx Answer 16433) Information on support for multiple MAC FIRs with different COE files in the same project.
  • (Xilinx Answer 16106) Back-annotated Verilog simulation causes memory collision errors.
  • (Xilinx Answer 14202) COE errors reported in wrong format.
  • (Xilinx Answer 20307) Some bitwidths fail to allow core to implement.
  • (Xilinx Answer 29314) Why does the output of my decimate by 2 Half-Band MAC FIR go to undefined when simulating a FIR filter for a Spartan-3/3E/3A/3AN device?
  • (Xilinx Answer 29452) Why do I see a map error when the SCLR option is not selected and tying to implement a Multiply Accumulate based Filer Architecture for Spartan-II/-IIE/-3/-3E/-3A or Virtex/-E/-II/-II Pro?
  • (Xilinx Answer 24680) Why is symmetry not exploited for the Multiply Accumulate Filter Architecture with Symmetric Coefficient Structure for an Interpolating filter and targeting a Virtex/-E/-II/-II Pro, or a Spartan-II/-IIE/-3/-3E/-3A device?
  • (Xilinx Answer 29454) Why is the impulse response wrong for the Multiply Accumulate Filter Architecture with Symmetric Coefficient Structure for an Interpolating filter targeting a Virtex/-E/-II/-II Pro or a Spartan-II/-IIE/-3/-3E/-3A device?
  • (Xilinx Answer 29453) Why do I see really long generation times when I try to target a Fixed Fractional Rate filter for Spartan-II/-IIE/-3/-3E/-3A or Virtex/-E/-II/-II Pro?
  • (Xilinx Answer 29048) Why does the core generation process hang when generating a fractional rate filter for a Virtex-II/-II Pro or Spartan-3/-3A/-3AN device?
  • (Xilinx Answer 29045) Why does the FIR Compiler appear to hang when the Synchronous Clear (SCLR) option is not selected and targets a Virtex-II/-II Pro or Spartan-3/-3A/-3AN device?

    LogiCORE IP FIR Compiler v2.0
    Initial Release in ISE Design Suite 8.2i IP Update 2.

    New Features

    • Support added for Virtex-5 and automotive variants of Virtex-4 and Spartan-3 devices
    • Support added for ISE 8.2i
    • Exploits symmetry in most multi-rate filter implementations to reduce resource utilization
    • Quantization of real value coefficients, and plotting of ideal and quantized frequency response
    • Supports fixed P/Q re-sampling filter implementations
    • Supports wider ranges for channel and rate parameters
    • Enhanced support for Virtex-4 and Virtex-5 families:
      • Support for MAC-based Hilbert and Interpolated filter structures
      • Core latency and resource estimation for DSP slices and block RAM now reported in the customization GUI
    Bug Fixes
    • CR 223807: CORE Generator reports Error:sim:57. This issue arises when the ratio of clock frequency to sample frequency is significantly larger than the number of cycles required to perform the filter calculation, resulting in a synthesis error and failure to generate the core. See (Xilinx Answer 22675) for further information.
    • CR 226141: ND signal does not operate as specified for single channel, fully parallel implementations, single rate half-band cases, or multi-channel decimating half-band filters. See (Xilinx Answer 23139) (Xilinx Answer 23088) or (Xilinx Answer 23091) for further information.
    • CR 224243: Failure to generate single rate or interpolating half-band filter implementations when fully parallel architecture is used. See (Xilinx Answer 22705) for further information.
    • CR 227184: Glitching might occur during switch-over between half-band coefficient sets, resulting in the center coefficient of the new half-band filter set being applied too early.
    Known Issues
    • (Xilinx Answer 14202) In the GUI, an error that reports an invalid parameter in the COE file is displayed in a different base format.
    • (Xilinx Answer 24317) Why does FIR Compiler, Floating Point Operator, and Fast Fourier Transform error when attempting to customize them on Solaris?
    • (Xilinx Answer 29423) Why does the FIR Compiler fail when I try to use a COE file that used to work with the MAC FIR or Distributed Arithmetic FIR?
    Distributed Arithmetic Filter Architecture: Multiply Accumulator Filter Architecture for all devices other than Virtex-4 and Virtex-5:
    • (Xilinx Answer 22706) Why does my single-rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"?
    • (Xilinx Answer 16433) Information on support for multiple MAC FIRs with different COE files in the same project.
    • (Xilinx Answer 16106) Back-annotated Verilog simulation causes memory collision errors.
    • (Xilinx Answer 14202) COE errors reported in wrong format.
    • (Xilinx Answer 20307) Some bitwidths fail to allow core to implement.
    • (Xilinx Answer 24680) Why is symmetry not exploited for the Multiply Accumulate Filter Architecture with Symmetric Coefficient Structure for an Interpolating filter which targets a Virtex/-E/-II/-II Pro or a Spartan-II/-IIE/-3/-3E/-3A device?
    • (Xilinx Answer 29454) Why is the impulse response wrong for the Multiply Accumulate Filter Architecture with Symmetric Coefficient Structure for an Interpolating filter and targeting a Virtex/-E/-II/-II Pro, and Spartan-II/-IIE/-3/-3E/-3A device?

      LogiCORE IP FIR Compiler v1.0
      Initial Release in ISE Design Suite 8.1i IP Update 1.

      New Features

      • First release
      • Consolidated interface for generation of most FIR filter implementations
      • Incorporates functionality of MAC_FIR_V5_1 and DA_FIR_V9_0 cores
      Bug Fixes
      • N/A
      Known Issues
      • (Xilinx Answer 22674) How do I determine the latency of my filter?
      • (Xilinx Answer 22673) Why does the FIR Compiler GUI crash when I enter an invalid Sample Frequency, or leave the Sample Frequency field empty?
      • (Xilinx Answer 22705) Why does my single-rate or interpolating half-band fully parallel filter fail to generate for Virtex-4 FPGA?
      • (Xilinx Answer 22706) Why does my single rate MAC FIR filter fail to generate, giving me an empty or missing netlist and "ERROR:sim - NgdBuild:153" or "ERROR:NgdBuild:604"?
      • (Xilinx Answer 22675) Why do I receive an "Error:sim:57" when trying to generate a MAC FIR?
      • Why can I not use the multi-column support when my coefficients are symmetrical?
      • (Xilinx Answer 29421) Why do I see a glitch when switching between coefficient sets with halfband filters?
      • (Xilinx Answer 29423) Why does the FIR Compiler fail when I try to use a COE file that used to work with the MAC FIR or Distributed Arithmetic FIR?

      Linked Answer Records

      Child Answer Records

      Answer Number Answer Title Version Found Version Resolved
      42260 LogiCORE FIR Compiler v6.2 - Patch Updates for the FIR Compiler N/A N/A
      41707 LogiCORE FIR Compiler v6.2 - Why is the output for a Fractional Rate in bursts, rather than at regular intervals? N/A N/A
      41591 LogiCORE FIR Compiler v6.2 - How to Line Up Input Data with the Correct Channel N/A N/A
      40769 LogiCORE FIR Compiler v6.0 - Why does my multi-column FIR Compiler implementation fail to route? N/A N/A
      40200 LogiCORE FIR Compiler v6.0 - My core simulation does not match the Latency value in the CORE Generator GUI. Why is that? N/A N/A
      35786 LogiCORE FIR Compiler v5.0 - Why does the reloadable DA FIR architecture fail to generate with a RAMB16 error when targeting Spartan-6? N/A N/A
      34149 LogiCORE FIR Compiler - When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device? N/A N/A
      42305 LogiCORE FIR Compiler v6.2 - Why do I see errors on the event interface for my multi-channel FIR, even when the data is properly aligned? N/A N/A
      42727 LogiCORE FIR Compiler v6.1 - Why does the output shift channels when using a multi-channel, interpolate by 2, odd number of symetrical coefficients, with oversample rate of 3 with Block RAM selected for memory FIR Compiler implementation? N/A N/A
      58579 LogiCORE FIR Compiler v5.0 - Why do I see a glitch on the output after a coefficient reload, when using the DA FIR implementation? N/A N/A

      Associated Answer Records

      Answer Number Answer Title Version Found Version Resolved
      43299 FIR Compiler v6.2 - Why does a symmetrical interpolation filter use more DSP48 slices when the coefficients are >=18 bits in Spartan-6? N/A N/A
      42727 LogiCORE FIR Compiler v6.1 - Why does the output shift channels when using a multi-channel, interpolate by 2, odd number of symetrical coefficients, with oversample rate of 3 with Block RAM selected for memory FIR Compiler implementation? N/A N/A
      42305 LogiCORE FIR Compiler v6.2 - Why do I see errors on the event interface for my multi-channel FIR, even when the data is properly aligned? N/A N/A
      42260 LogiCORE FIR Compiler v6.2 - Patch Updates for the FIR Compiler N/A N/A
      41707 LogiCORE FIR Compiler v6.2 - Why is the output for a Fractional Rate in bursts, rather than at regular intervals? N/A N/A
      41591 LogiCORE FIR Compiler v6.2 - How to Line Up Input Data with the Correct Channel N/A N/A
      40200 LogiCORE FIR Compiler v6.0 - My core simulation does not match the Latency value in the CORE Generator GUI. Why is that? N/A N/A
      35786 LogiCORE FIR Compiler v5.0 - Why does the reloadable DA FIR architecture fail to generate with a RAMB16 error when targeting Spartan-6? N/A N/A
      34149 LogiCORE FIR Compiler - When I build a reloadable Transpose FIR structure, why do I see a difference between my behavioural and post-par simulation results when targeting a Spartan-3A DSP device? N/A N/A
      32947 LogiCORE FIR Compiler v5.0 - Why is the GUI so slow, when changing the coefficient vector field? N/A N/A
      32344 LogiCORE FIR Compiler v4.0 - How do I access the reload order information when using the FIR Compiler v4.0 in System Generator for DSP? N/A N/A
      32300 LogiCORE FIR Compiler v4.0 - Why does the FIR Compiler fail to generate core if the total number coeffients is more than 34816? N/A N/A
      31996 LogiCORE FIR Compiler v4.0 - When the "Generate chan_in value in advance" parameter is used, why is the chan_in output delayed by the specified number of cycles, rather than being output early by the specified number of cycles? N/A N/A
      31841 LogiCORE FIR Compiler v4.0 - Why does the FIR Compiler fail to generate with an out of memory error for a filter that generated without any problems in FIR Compiler v3.2? N/A N/A
      5366 LogiCORE MAC FIR Filter, DA FIR Filter, FIR Compiler - How do I convert floating-point coefficients to fixed-point for Xilinx DA and MAC FIR filters? N/A N/A
      54502 IP Release Notes and Known Issues for LogiCORE IP FIR Compiler core for Vivado 2013.1 and newer tools N/A N/A
      AR# 29138
      Date Created 09/04/2007
      Last Updated 12/23/2014
      Status Active
      Type Release Notes
      IP
      • FIR Compiler