Keywords: coherency, DMA, master
I have a design where I am doing DMA transfer from my PLB master IP to external memory and vice versa.
The DMA works fine, but only if I disable cache. If I enable cache, it does not work.
Make sure that the cache coherency issue has been ruled out.
Please refer to the PowerPC Reference Guide for more information on cache coherency.
When initializing your source and destination buffer, flush your cache line to avoid cache coherency after each initialization. The following code snippet provides an illustration:
set_data_buffer(src_buffer, 64, 5);
XCache_FlushDCacheLine(src_buffer);
set_data_buffer(dst_buffer, 64, 0);
XCache_FlushDCacheLine(dst_buffer);