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AR# 29159

LogiCORE IP RapidIO - Generating an example design for use with the ML505/ML605/SP605 development boards


Can the example design generated with the Serial RapidIO core be targeted specifically to the ML505, ML605, or SP605 boards?


The Serial RapidIO v5.5 and later can easily be generated and implemented to specifically target the ML505, ML605, and SP605 development boards. This allows for a simple demonstration of the core's capabilities.

First, the Serial RapidIO Core must be generated using the CORE Generator tool. To generate a Serial RapidIO example design for one of these demo boards,perform the following:

  1. Depending on which demo board you are targeting, generate a core with component name prefix that matches one of the following: "ml505_" or "ml605_" or "sp605_".
    • Note that the prefix is case sensitive; the first two letters must be lower-case.
    • For example, naming the core "sp605_srio_v5_6" results in the proper output, but "SP605_srio_v5_6" does not work.
  2. Select 1x mode, and set the rest of the parameters as default. The generated UCFhas the correct pinout (but not the correct comments) for the targeted demo board.
  3. Run "implement.bat" or "implement.sh" in the "implement" directory to get a ".bit" file.

ML505 Setup

NOTE: The ML505 has only one set of SMA connectors, therefore, it can only support the 1x core. If you try to generate a 4x core with the "ml505_*" component name, you will get a UCF generated for the ML523. If you have the ML523 board, you can try that as well, just use the switches mentioned in the Getting Started Guide (UG247), Table 5-14.

Next, you need to prepare the ML505 board:

  1. Position the ML505 board so the Xilinx logo is in the lower left corner.
  2. Make sure the power switch in the upper right corner is in the OFF position.
  3. Connect the AC power cord to the power supply brick. Plug the power supply adapter cable into the ML50x board. Plug in the power supply to AC power.
  4. Connect two SMA connectors between J42, J43, J44, and J45 to loopback the RapidIO data. RXN should connect to TXN, and RXP to TXP.
  5. Connect a Platform USB cable to your computer, and then connect its JTAG cable to the PC4 connector on the board (next to the SFP cage, upper left).
  6. Turn on the ML505 board's main power switch.
Next, the RapidIO Example Design bitfile, created by running the "implement.bat" script, is loaded onto the ML505:
  1. Start iMPACT and enter Boundary Scan mode.
  2. Right-click and Initialize JTAG chain.
  3. Bypass all devices in the chain, except for the Virtex-5 FPGA.
  4. Assign the BIT file you created from the "implement.bat" file to the FPGA.
  5. Right-click the FGPA and select Program, and use the default programming options.
  6. The design should now be loaded up. You can check this based on the LEDs below.
To understand what the board is doing and how to apply stimulus to the design, the ML505 has various switches and LEDs. Following is what each switch and LED on the board does:


Sw13 = link_reset
Sw14 = local_reset
Sw11 = load
Sw10 = go

The DIP switches are all found on SW8 on the board (located bottom-right):

Dip[1] = NREAD
Dip[2] = NWRITE
Dip[3] = NWRITE_R
Dip[4] = SWRITE
Dip[5:6] = Size of transactions to send
Dip[7:8] = Number of transaction sequences to send

The LEDs (called GPI/O) are located along the bottom edge of the board, below the LCD screen:

GPIO[0] = error
GPIO[1] = DCM_Lock
GPIO[2] = PLL_Locked
GPIO[3] = lnk_porterr_n (LED lit = no error)
GPIO[4] = port_initailized
GPIO[5] = ~lnk_rrdy_n (LED lit = receive ready)
GPIO[6] = ~lnk_trdy_n (LED lit = receive ready)
GPIO[7] = 1'b1

For the LEDs, once the design has been loaded you should see GPIO[7:1] lit, with GPIO[0] dark. If you see otherwise, something has gone wrong with your setup.

At this point, once you have the design running successfully, there is not much to see on the board except the LED status lights. To see the actual transactions, you need either a RapidIO link analyzer that you can connect in the loopback, or you can put a ChipScope core into the design to take a look at the transactions from the User Application side of the core. ChipScope is an ideal way to become familiar with the core's interface.

ML605/SP605 Setup

The setup for the ML605 and SP605 boardsare similar to the ML505. However, there is no on-board clock, so a clock will have to be provided from another source via SMA cables. If you also have an ML505, that can be used to provide the clock via SMA. The board demonstration designs were tested using an ML605 to output a clock via SMA.

For assistance, see the Board Documentation at:
ML605 Documentation
SP605 Documentation
AR# 29159
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article
  • Spartan-6 LXT
  • Virtex-5 LXT
  • Virtex-6 LXT
  • Serial RapidIO