Keywords: CORE Generator, #1, open, basestation, architecture, initiative, Virtex-5, Virtex5, v5
When simulating a design with OBSAI core, warnings similar to the following might occur:
"# ** Error: Error : PLL_ADV input DI is set toUUUUUUUU00UUUUUU . The bit 15 to 8 need to be set to 00h at address DADDR = 11100.
#
# Time: 7420 ns Iteration: 1 Instance: /tc_basic_om/tb/incgtpgen1/uut_c1/gtp_and_clocks_i/tx_clk_gen_i/pll_i
# ** Warning: Warning : Address DADDR=81 on the DCM_ADV instance is unsupported.
#
# Time: 7420 ns Iteration: 1 Instance: /tc_basic_om/tb/incgtpgen1/uut_c1/gtp_and_clocks_i/rx_clk_gen_i/dcm_i
# ** Error: Error : PLL_ADV input DI is set toUUUUUUUU00UUUUUU . The bit 15 to 8 need to be set to 00h at address DADDR = 11100.
#
# Time: 7420 ns Iteration: 1 Instance: /tc_basic_om/tb/g_core2/incgtpgen2/uut_c2/gtp_and_clocks_i/tx_clk_gen_i/pll_i
# ** Warning: Warning : Address DADDR=81 on the DCM_ADV instance is unsupported."