11.3 System Generator for DSP - Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

AR#	29170	Search For Another Answer
Topic	SW-SysGen
Last Updated	09/10/2009
Status	Active

Description

Keywords: SysGen, not matching, mismatch, Synplify Pro, Behavioral simulation

Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

Solution

This can be caused by a known issue in which Synplify and Synplify Pro incorrectly optimize constants that drive shift register delay lines such that the delay is removed and the constant value is presented earlier than intended.