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AR# 29170

11.3 System Generator for DSP - Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

Description

Why do I see simulation mismatches at the beginning of my HDL simulation generated from System Generator for DSP if Synplify is used for synthesis?

Solution

This can be caused by a known issue in which Synplify and Synplify Pro incorrectly optimize constants that drive shift register delay lines such that the delay is removed and the constant value is presented earlier than intended.

AR# 29170
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article