The timing simulation model for the GTP_DUAL in ISE 9.2.02 contains a bug that can cause the GTP RX interface to output Xs in Verilog timing simulation. The failures will occur only in timing simulations that include the GTP_DUAL and only when using ISE 9.2.02. Behavioral simulation is not affected. This Answer Record contains a patch to fix GTP timing simulation in ISE 9.2.02.
To install the patch.
1. Backup the X_GTP_DUAL.v file in the %Xilinx%\verilog\src\simprims directory in a temporary directory.
2. Download the patched file here:
http://www.xilinx.com/txpatches/pub/utilities/fpga/ar_24367_patch.zip
3. Overwrite X_GTP_DUAL.v in the %Xilinx%\verilog\src\simprims directory with the patched file.
4. Re-run COMPXLIB.
Alternatively, you can compile the patched X_GTP_DUAL.v directly into your simulation. For example, in ModelSim add the line vlog -work simprims_ver X_GTP_DUAL.v to your .do script.