For FIFOs configured with standard read mode and that use embedded registers (which results in a read latency of 2 clk cycles), the following power up values are incorrect in the behavioral models:
1) Verilog behavioral model: DOUT and VALID powers up on 'x' and changes to '0' after the first clk edge
2) VHDL behavioral model: DOUT powers up on 'U' and changes to '0' after the first clk edge. VALID power ups correctly.
This issue is seen only in behavioral simulation. Please use structual simulation model instead of behavioral simulation. The structural model can be generated by selecting Core Generator GUI, under Project Option, Generation Tab.