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AR# 29192

9.2 sp2 -ERROR:Simulator:29 - at 0 ns : in cdr(Behavioral), file C:/projects/SPFT_Xilinx/clock_and_data_recovery/cdr.vhd:94: Default port map for entity phase_correction to component phase_correction connects SIGNED type local port half_period_bias of th

Description

When I ran a design which had the following hierarchy and contained the following statements, the error message below would appear. In this design a is the top level module. And b,c,d,e are submodules of a. f is a submodule of d.

a

/ | | \

b c d e

|

f

The following statements are in the top level VHDL file.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;

entity cdr is

port ( half_period_reg : in signed (11 downto 0););

end cdr;

The following statements are contained in submodule d.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

entity phase_correction is

port ( half_period_reg : in signed(11 downto 0);

half_period_bias : out signed(11 downto 0));

The following statements are included in submodule f.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_SIGNED.ALL;

use IEEE.NUMERIC_STD.ALL;

entity deadband is

port ( x : in signed(12 downto 0);

a : in signed (11 downto 0);

phase_error : out signed (12 downto 0));

end deadband;

ERROR:Simulator:29 - at 0 ns : in cdr(Behavioral), file (null): Default port map

for entity phase_correction to component phase_correction connects SIGNED

type local port half_period_bias of the component to SIGNED type port of the

entity.

Solution

To fix this error message, please remove the statements "use IEEE.STD_LOGIC_ARITH.ALL;"

AR# 29192
Date Created 08/16/2007
Last Updated 02/28/2010
Status Archive
Type General Article