When simulating the DCM both in functional and timing simulations, the DCM loses lock if the clock input stops momentarily (i.e., one clock cycle or longer). The CLK0 output of the DCM continues, but other outputs (e.g., CLKDV and CLKFX) are stopped and the DCM requires a reset to regain a lock.
This is a simulation model inconsistency only, and will be changed to match the hardware behavior in Service Pack 4 for ISE 9.2i design tools.
In hardware, the DCM will behave as described in the Virtex-5 Users Guide (UG190), in the "DCM Design Guidelines" section, under the heading "Input Clock Changes." Specifically, if the clock stops for less than 100 ms and is returned with the same phase as the original clock, the DCM will not lose lock and the clock outputs will return as expected.