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AR# 29203

9.1i Virtex-5 MAP- Placement Phase 6.2 crash when BUFR drives SYSMON component

Description

My design contains a SYSMON component that is driven by a Regional Clock Buffer (BUFR) and MAP crashes during placement phase 6.2. Is this a known problem with a work around? 

 

Note: The failing phase number may be "X.2" where X is any number.

Solution

This is a known problem, and it is specific to SYSMON components that are clocked by a BUFR. The problem is scheduled to be fixed in ISE version 10.1. Meanwhile, other than removing the SYSMON component, the way to work around it is to disable the Regional Clock Placer with an environment variable while manually constraining all Regional Clock Domains. 

 

To disable the Regional CLock Placer: 

 

Windows 

SET XIL_PAR_NOIORGLLOCCLKSPL=1 

 

Linux and Solaris 

set XIL_PAR_NOIORGLLOCCLKSPL 1 

 

For general information about setting ISE environment variables, see (Xilinx Answer 11630)

 

To manually constrain the BUFR domains, choose a BUFR site to LOC the clock buffer and then define an area group to constrain the BUFR clock domain to one or more clock regions, keeping in mind that the BUFR can only reach loads in the same or vertically adjacenent clock region. The area group is most easily defined using a Time Group based on the clock net name. 

 

Example: 

INST "INC_LIW_DEINT.vxp_out_capture_bufr" LOC = "BUFR_X1Y10" ; 

NET "liw_out_clk" TNM_NET = "TN_liw_out_clk" ; 

TIMEGRP "TN_liw_out_clk" AREA_GROUP = "CLKAG_liw_out_clk" ; 

AREA_GROUP "CLKAG_liw_out_clk" RANGE = CLOCKREGION_X1Y5, CLOCKREGION_X1Y4;

AR# 29203
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article