We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 29207

9.2 System Generator for DSP - Why does a "caught standard exception" error occur when generating a design containing the FIR Compiler v3.1?


When my design contains a FIR Compiler block with symmetric coefficients, a "standard exception" error occurs during netlist generation.


This error can occur if the FIR Compiler's supported data input width or coefficient width is exceeded. For filters with symmetric coefficients, the maximum bit width is one less than asymmetric coefficients because a pre-adder is used to take advantage of symmetry.

For Virtex-4 and Spartan-3A DSP, the maximum data bit width with symmetric coefficients is 17 bits. For Virtex-5, the maximum data bit width with symmetric coefficients is 24 bits.

The coefficient width cannot exceed 18 bits. For further details, refer to the FIR Compiler data sheet.

This error message will be improved in a future release of System Generator.

AR# 29207
Date 12/15/2012
Status Active
Type General Article