We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29208

Virtex-4 Aurora - Special reset consideration for Virtex-4 Aurora designs


This Answer Record details a special consideration when designing reset logic around the Aurora Core top level.


There are two resets that go in to the Virtex-4 Aurora Core:

1. RESET - This port resets the core logic and initialization state machines. It does not reset the MGTs. This reset port must be asserted synchronously to USER_CLK.

2. PMA_INIT - This port re-initializes the MGT by resetting the GT11_INIT blocks. Asserting this port will reset the MGTs and the Aurora Core initialization logic. This reset port must be asserted synchronously to INIT_CLK.

NOTE: These reset ports are not asynchronous. They must be asserted on the appropriate clock edge. RESET must be asserted synchronous to USER_CLK, and PMA_INIT must be asserted synchronous to INIT_CLK.

AR# 29208
Date Created 09/04/2007
Last Updated 12/15/2012
Status Active
Type General Article