Solution
General LogiCORE Fast Fourier Transform (FFT) Issues
LogiCORE Fast Fourier Transform (FFT) v8.0
Initial release in ISE Design Suite 12.3, Vivado 2012.1 tool.
New Features
- ISE 12.3 tool support
- AXI4-Streaming Interfaces
Resolved Issues
Known Issues (ISE)
Known Issues (Vivado)
- (Xilinx Answer 50907) Vivado Simulation - How do I use -novopt with the integrated ModelSim Simulation flow?
- (Xilinx Answer 50909) 2012.2 Vivado Simulator - Why do I receive errors or data mismatches when I attempt to simulate my IP in Vivado Simulator using the behavioral simulation flow?
- (Xilinx Answer 50877) Why do I get an error when using the FFT with floating-point interfaces and simulated in the Vivado simulation flow with ModelSim 10.1a?
- (Xilinx Answer 53465) 2012.4 Vivado Simulator - Why does my DSP Digital Communications core fail to simulate with error Error: Failed to find design work <Core name>?
LogiCORE Fast Fourier Transform (FFT) v7.1
Initial Release in ISE Design Suite 12.1.
New Features
- ISE 12.1 software support
Resolved Issues
Known Issues
LogiCORE Fast Fourier Transform (FFT) v7.0
Initial Release in ISE 11.2 design tools.
New Features
- ISE 11.2 software support
- Support for Virtex-6 and Spartan-6 devices
- Option to use LUTs to construct complex multipliers
- Configurable input data timing (no offset / three clock cycle offset
Bug Fixes
- CR479713 Resource counts may be wrong by a factor of 2 for Radix-4.
- CR493695, CR504822 Weblink in C Model tab has invalid URL.
- CR503204: After the URL is clicked, the text disappears and a blank page is shown until the GUI is reopened.
- Symptom: In the "Test" section of the characterization tables (Tables 7, 8, 9), entries 5 to 16 are incorrect.
- CR517653 Documentation for Radix-4, Radix-2, and Radix-2 Lite does not say what input formats they support.
- CR500087 Data sheet missing information about the simple round which takes place after complex multiplies.
- CR500986 FFT v6.0 fails under Virtex-4 special (Q, QR) families.
- CR492572 C model hangs for some floating point testcases.
- CR492647 C Model User Guide instructions for Linux are incorrect.
- CR492205 C Model User Guide doesn't mention ordering of input and output data
Known Issues
- (Xilinx Answer 32405) LogiCORE Fast Fourier Transform (FFT) - Where can I download older versions of the FFT C Model?
- (Xilinx Answer 35366)LogiCORE Fast Fourier Transform (FFT) v7.0 - Why do I get a MAP error about a BRAM if I use Spartan-6 Device?
LogiCORE Fast Fourier Transform (FFT) v6.0
Initial release in ISE 10.1 IP Update 3.
New Features
- ISE 10.1 software support
- Increased data and phase factor precision to 34 bits
- Added support for Block Floating Point in the Pipelined, Streaming I/O architecture
- IEEE single precision floating point support
Resolved Issues
- CR451474 FFT data sheet incorrectly states that C_CHANNELS is a generic required for the C model
Symptom: The C_CHANNELS generic was present in the table of generics, but not required
- CR451971 Finite Word Length Considerations should describe the output width formula in more detail
Symptom: Missing information
- CR455207 FFT 5.0 - One option in page 3 always greys out if implementation is Automatically Select
Symptom: When using the Automatically Select architecture option and the implementation selected is Pipelined, Streaming I/O, the Number of Stages using Block RAM is grayed-out and displays a red zero
Work-around: Select Pipelined, Streaming I/O architecture directly rather than using Automatically Select
- CR470372 FFT v5.0 - Control Logic Priority not documented
Symptom: CE/SCLR priority is not documented
- CR476344 Data sheet does not have information on clock enable usage
Symptom: Behavior of clock enable (true pause or stops only part of the core)
- CR471437 Simulation mismatch for multichannel Radix-2 testcase after reset
Symptom: Corruption of output data frame versus C model output
- CR474735 Request to add details about overflow handling between butterfly stages
Symptom: Data sheet does not discuss state of data after overflow occurs
- CR473116 FFT v5.0 - Data sheet description of convergent rounding is incorrect
Symptom: Rounding scheme employed by the core does not match data sheet description
- CR471439 Incorrect point size values in Virtex-5 and Virtex-4 performance tables
Symptom: Wrong data for CT Scanner point size entries 15 and 16
Known Issues
- (Xilinx Answer 24318) Why does the Fast Fourier Transform Core take so long to generate?
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device
- (Xilinx Answer 30108) Why do the data sheet Performance and Utilization numbers seem to under-perform previous versions?
- (Xilinx Answer 32002) How is the rounding between butterfly stages handled for the FFT?
- (Xilinx Answer 32341) When clicking on the C-Model Link in the C-Model tab, in 11.1, why does the text disappear?
- (Xilinx Answer 32391) When using the C Model, to simulate a pipelined streaming FFT with convergent rounding, why do I see: ERROR:c_model:to_hex: input val 1 is out of range -1 to <+1>?
- (Xilinx Answer 32395) When targeting a Radix-4 implementation, why is the resource count in the GUI more than what I see in the MAP report?
- (Xilinx Answer 32403) Why do the Linux C Model compilation instructions in the User Guide give an error?
LogiCORE Fast Fourier Transform (FFT) v5.0
Initial Release in ISE 9.2i IP Update 2
New Features
- ISE 9.2i software support
- Fixed Point Bit-True C Model
- Programmable Cyclic Prefix Insertion for OFDM systems
- Reduced Memory on natural order output for Streaming FFT
- Multi-Channel Support for Radix-2 Loop Engine and Radix-4 Loop Engine
- FWD/INV control for each channel in multi-channel mode
- Latency feedback in CORE Generator GUI
- Improved clock frequency and resource usage
Resolved Issues
- CR437634 Data-dependent failure for 3-DSP complex mult in streaming architecture
Data samples would appear swapped in some cases
Work-around was to use fast complex multipliers (4 DSP48s)
- CR436649 FFT GUI should mention that the block RAM count is in terms of 18K block RAMs
For Virtex-5, the CORE Generator FFT GUI did not indicate if 36K or 18K block RAMs were being reported
- CR434883 Maximum throughput value/limit should change when multichannel FFT is selected
For multi-channel FFTs, only the Radix-2 Lite architecture was supported and the maximum throughput should have been scaled accordingly to 25 MSPS
- CR434679 Spartan-3A DSP DSP48A butterfly could implement 48-bit add, but currently does not
The DSP48A (speed optimized) butterflies for Spartan-3A DSP supported only 30-bit adder-subtractors rather than the possible 48-bit adder-subtractors
- CR434515 DSP48A-based 52x18 complex multiplier is unroutable
The Spartan-3A DSP DSP48A 52x18 complex multiplier (used in some unscaled FFTs) could not be routed because of a conflict on the cascade routing between DSP blocks
- CR434329 OVFLO mismatch for streaming architecture
The overflow output from the streaming FFT architecture could arrive one cycle later than the output data frame
- CR434202 Very large Virtex-4-based FFTs fail in MAP because XST adds buffers on block RAM WE lines
Large FFTs utilizing over 250 block RAMs in Virtex-4 failed to MAP because of buffers being inserted on high fanout nets
- CR431156 FFT v4.0 - Option to tie unused logic high/low
Butterfly stages in the streaming architecture continued to pass data even when they were bypassed, leading to higher dynamic power
The butterfly stage inputs are now gated to pass zeros when they are not processing data
- CR437828 FFT - Request to be able to specify memory type for "natural order" buffering
The user previously had no control over whether distributed RAM or block RAM was used to implement the reorder buffer for natural-order output streaming FFTs
This is now an option in the CORE Generator FFT GUI
- CR440845 FFT v4.1 - Request to add link to synthesis and simulation guide to data sheet
Users were not aware that simulator resolution for UniSim behavioral models had to be set to 1 ps. Incorrect behavior was seen when the simulator resolution was 1 ns.
- CR437975 Large FFT requires large amounts of memory
FFT cores above 4096 points could take a very long time to generate or cause CORE Generator to run out of memory
Known Issues
- (Xilinx Answer 24318) Why does the Fast Fourier Transform Core take so long to generate?
- (Xilinx Answer 29555) Why do FFTs with large complex multipliers fail in PAR when targeting a Spartan-3A DSP device?
- (Xilinx Answer 29556) Why do I receive a 9.2.03i PAR Segmentation Fault, when implementing a Virtex-5 Streaming Architecture, with larger multipliers?
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix 2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29563) Why does the data sheet mention that the C Model uses the C_CHANNELS generic?
- (Xilinx Answer 29848) Why does declaring the xfft_v5_0_bitacc_cmodel.h in multiple files cause an error during the linking stage of the C-Model compilation?
- (Xilinx Answer 29858) Why is the "Number of Stages using Block RAM" option on page 3 of the GUI grayed out, when the Implementation Option on page 1 is set to Automatic?
- (Xilinx Answer 29984) Why is the output of the FFT v5.0 bit for bit not identical to the output of the FFT v3.2, v4.0 or v4.1, when using one of the burst architectures?
- (Xilinx Answer 30093) Why does the FFT C-Model mex function error out in my version of MATLAB?
- (Xilinx Answer 30108) Why do the data sheet Performance and Utilization numbers seem to under-perform previous versions?
- (Xilinx Answer 30937) Why does the description of the convergent rounding appear to be opposite of the conventional implementation of convergent rounding (round-to-even)?
- (Xilinx Answer 31154) How do I use the C-Model Scaling Schedule, or why do I receive an error about the final stage of my Radix-4, Burst I/O or Pipelined, Streaming I/O architectures, when setting the scaling schedule?
- (Xilinx Answer 32002) How is the rounding between butterfly stages handled for the FFT?
- (Xilinx Answer 32391) When using the C Model, to simulate a pipelined streaming FFT with convergent rounding, why do I see: "ERROR:c_model:to_hex: input val 1 is out of range -1 to < +1 >"?
LogiCORE Fast Fourier Transform (FFT) v4.1 rev1
Initial Release in ISE 9.1i IP Update 2
New Features
- Spartan-3A DSP support added
Resolved Issues
Known Issues
LogiCORE Fast Fourier Transform (FFT) v4.1
Initial Release in ISE 9.1i IP Update 1
New Features
Bug Fixes
- CR430617: Radix-2-Lite architecture data mismatch when BFP used
- CR430722: Output data mismatch when using 52x18 complex multiplier configuration
- CR430131: Timing diagrams for Burst-I/O solutions with natural-order output are misleading
- CR430302: FFT v4.0 data sheet has some incorrect performance and resource utilization data
- CR429986: Minor errors in data sheet diagrams
- CR429769: Exception reported when generating core
Known Issues
- (Xilinx Answer 24317) Why do FIR Compiler, Floating Point Operator, and Fast Fourier Transform error out when attempting to customize them on Solaris?
- (Xilinx Answer 24318) Why does the Fast Fourier Transform Core take so long to generate?
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 24437) Why is the multiplier usage always zero when targeting Virtex-II/-II Pro, Spartan-3/-3E/-3A?
- (Xilinx Answer 29237) Why do I see a degradation in the signal-to-noise ratio of the slot test, near the edges of the transform?
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29555) Why do FFTs with large complex multipliers fail in PAR when targeting a Spartan-3A DSP device?
- (Xilinx Answer 29556) Why do I receive a 9.2.03i PAR segmentation fault when implementing a Virtex-5 Streaming Architecture, with larger multipliers?
- (Xilinx Answer 29560) Why does the overflow flag not assert when an overflow occurs in my 64- or 128-point FFT?
- (Xilinx Answer 30937) Why does the description of the convergent rounding appear to be opposite of the conventional implementation of convergent rounding (round-to-even)?
LogiCORE Fast Fourier Transform (FFT) v4.0
Initial release in ISE 8.2i IP Update 3.
New Features
- Support for Virtex-5FPGA
- Addition of Radix-2-lite architecture offering lowest-yet resource solution
- Addition of multi-channel support for Radix-2-lite architecture
- Removal of latching behavior for START and UNLOAD signals
- New data-driven GUI
Bug Fixes
- CR 325636 - Invalid frame after double reset event
- CR 332201 - Failure to generate the core because of multi-source signals
Known Issues
- (Xilinx Answer 24317) Why do FIR Compiler, Floating Point Operator, and Fast Fourier Transform error when attempting to customize them on Solaris?
- (Xilinx Answer 24318) Why does the Fast Fourier Transform Core take so long to generate?
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 24437) Why is the multiplier usage always zero when targeting Virtex-II/-II Pro, Spartan-3/-3E/-3A?
- (Xilinx Answer 24463) Why are my results wrong when I use the Radix-2 Lite implementation, with the block floating point option?
- (Xilinx Answer 29427) Why do I see incorrect outputs when I simulate an unscaled FFT with a point size of larger than 1024, and I have the Complex Multiplier Optimize for Speed option selected?
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29451) Why can I not achieve the performance and area number for some of the architectures as listed in the data sheet?
- (Xilinx Answer 29560) Why does the overflow flag not assert when an overflow occurs in my 64- or 128-point FFT?
- (Xilinx Answer 30937) Why does the description of the convergent rounding appear to be opposite of the conventional implementation of convergent rounding (round-to-even)?
LogiCORE Fast Fourier Transform (xFFT) v3.2/patch 1
Initial release in ISE 8.1i IP Update 1.
New Features
Bug Fixes
- CR 220574: For the Pipelined Streaming I/O architecture, overflow is signaled for frames with no overflow, preceding or following a frame with an overflow (overflow tainting next or previous frame)
- CR 220203: GUI displays incorrect resource estimates for DSP48 count
- CR 220655: For the Pipelined Streamlining I/O architecture, the core dumps incorrect output data after a reset event (SCLR asserted, or new NFFT value latched in). If two reset events occur less than ~40 CLK cycles apart, the second reset might be incomplete and the core might start generating output values (DV = 1) from an incomplete input frame
Known Issues
- (Xilinx Answer 21988) Large FFT point size generation times.
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 21989) Slice estimate and implementation results are different.
- (Xilinx Answer 29420) Why do I see the Run-Time configurable option for an 8-point FFT only when I recustomize the core?
- (Xilinx Answer 24436) Why is the first data frame after a multi-cycle reset is incorrect?
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29449) Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals?
- (Xilinx Answer 29561) Why do my FFT output results drift from the expected results and become increasingly more inaccurate the longer I simulate my design?
- (Xilinx Answer 29562) Why does the Number Of Block RAM Per Stage parameter always reset to zero ("0") when I recustomize my core?
- (Xilinx Answer 30937) Why does the description of the convergent rounding appear to be opposite of the conventional implementation of convergent rounding (round-to-even)?
LogiCORE Fast Fourier Transform (FFT) v3.2
Initial release in ISE 7.1i IP Update 3.
New Features
- Support added for Spartan-3EFPGA
- "Optimize for Speed using Xtreme DSP Slices" option added to all three architectures. This option in Virtex-4 FPGA enables operation of the core at higher clock speeds by using more DSP48s. This provides another way to make trade-offs between resource utilization and performance.
- "Bit/Digit Reversed Order" or "Natural Order" output available for all three architectures.
- "Input Data Width" and "Phase Factor Width" expanded to include all values from 8 to 24.
- "Run Time Configurable Transform Length" available for all three architectures.
- "Distributed RAM Memory Option" available for Data for Radix-4 Burst I/O as well as Radix-2 Minimum Resources.
Bug Fixes
- CR 199541: Incorrect FFT output results for Radix-4 Burst I/O when using Virtex-4
- CR 201500: Core will not generate for these two cases:
- When either the Radix-4 Burst I/O or Radix-2 Minimum Resources architectures are selected and output width = 35 bits with phase factor width = 20 or 24 bits
- When the Pipelined Streaming I/O architecture is selected and output width > 35 bits with phase factor width = 20 or 24 bits
- CR 201885: If either Radix-4 Burst I/O or Radix-2 Minimum Resources are selected, the core will not begin processing after the initial triggering of START unless SCLR is asserted first
- CR 207964: Maximum clock speed numbers in data sheet v3.1 have been corrected in v3.2
- CR 209462: VHDL and Verilog Structural Behavioral models give incorrect results
Known Issues
- (Xilinx Answer 21988) Large FFT point size generation times.
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 21989) Slice estimate and implementation results are different.
- (Xilinx Answer 29420) Why do I see the Run-Time configurable option for an 8 point FFT only when I recustomize the core?
- (Xilinx Answer 24436) Why is the first data frame after a multi-cycle reset is incorrect?
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or why do I see differences between the Radix 2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29449) Why do the timing diagrams not show the 3 clock cycle delay of the indexing signals?
- (Xilinx Answer 29051) Why does the Verilog simulation model output does not match the timing shown in the FFT data sheet?
- (Xilinx Answer 29561) Why do my FFT output results drift from the expected results and become increasingly more inaccurate the longer I simulate my design?
- (Xilinx Answer 29562) Why does my the Number Of Block RAM Per Stage parameter always reset to zero ("0") when I recustomize my core?
- (Xilinx Answer 30937) Why does the description of the convergent rounding appear to be opposite of the conventional implementation of convergent rounding (round-to-even)?
LogiCORE Fast Fourier Transform (FFT) v3.1
Initial release in ISE 6.3i IP Update 4.
New Features
- "Optimize for Speed Using XtremeDSP Slices" option in Virtex-4 enables operation of the core at higher clock speeds by utilizing more DSP48s. This gives you an additional option for making trade-offs between resource utilization and performance.
- Maximum clock speed has been increased for all supported FPGA families.
Bug Fixes
- CR 199541 - Incorrect FFT output results for Radix-4 Burst I/O when using Virtex-4
- CR 201500 - Core will not generate for Radix-4 Burst I/O and Radix-2 Minimum Resources when output width = 35 bits with phase factor width = 20 or 24 bits and for Pipelined Streaming I/O when output width > 35 bits with phase factor width = 20 or 24 bits
- CR 201885 - At the very beginning, Radix-4 Burst I/O and Radix-2 Minimum Resources will not begin processing when START is asserted unless SCLR is asserted first
Known Issues
- (Xilinx Answer 21453) Virtex-4 FPGA speed numbers in the data sheet are incorrect.
- (Xilinx Answer 20717) Streaming I/O mode might occasionally have memory collisions.
- (Xilinx Answer 20307) Placement Issues when targeting a Virtex-II, Virtex-II Pro, or Spartan-3 device.
- (Xilinx Answer 21453) Virtex-4 FPGA speed numbers in the data sheet are incorrect.
- (Xilinx Answer 23247) Why are the output results of the Pipelined Streaming I/O xFFT architecture not symmetrical? Or, why do I see differences between the Radix-2 Minimum Resource implementation and the Pipelined Streaming I/O FFT implementation?
- (Xilinx Answer 29051) Why does the Verilog simulation model output not match the timing shown in the FFT data sheet?
- (Xilinx Answer 29557) Why are the output results of my Pipelined Streaming FFT incorrect?
- (Xilinx Answer 11155) I cannot find the Verilog behavioral simulation mode for the FFT. When performing a Verilog behavioral simulation an error occurs: "Error: (vsim-3033) ... The design unit was not found"
Issues resolved in xFFT v3.1 patch
LogiCORE Fast Fourier Transform (FFT) v3.0
Initial release in ISE 6.3i IP Update 2.
New Features
- Support added for Virtex-4FPGA
- New pipelined streaming I/O architecture uses less memory
- Point sizes extended from 8 to 64k
Bug Fixes
Known Issues
LogiCORE Fast Fourier Transform (FFT) v2.1
Initial release in ISE 6.1i IP Update 1.
New Features
Bug Fixes
- CR 177866: MAP warning due to carry chain being broken after placement
- CR 178678: scale_sch width incorrect in VHDL behavioral model
- CR 175648, 175644: Overflow incorrectly reported
- CR 177048: Default scaling schedule incorrect for Radix-4 Burst I/O
Known Issues
LogiCORE Fast Fourier Transform (FFT) v2.0
Initial release in ISE 5.xi IP Update 2.
The Fast Fourier Transform (FFT) v2.0 is a new core which should be used in new Virtex-II, Virtex-II Pro, and Spartan-3 FPGA designs. The FFT v2.0 core supersedes the 64-256-1024-Pt Complex Fast Fourier Transform core v1.1, but is not a direct drop-in replacement.
New Features
The following features in the new Fast Fourier Transform core v2.0 are new relative to all versions of the 64-256-1024-Pt Complex Fast Fourier Transform core:
- Supports Virtex-II, Virtex-II Pro, and Spartan-3 FPGAs
- Supports transform sizes ranging from 16 to 16384 points
- Selectable Data Sample precision: 8, 12, 16, 20 or 24 bits
- Selectable Phase Factor precision: 8, 12, 16, 20 or 24 bits
- Supports three arithmetic types:
- Unscaled (full precision) fixed point
- Scaled fixed point
- Block floating point
- Option to specify either block RAM or distributed RAM for data or phase factor storage
- A choice of 3 architectures offers users the ability to trade-off between transform time and core size
When compared to all versions of the following cores:
- 32-Point Parameterizable Complex Fast Fourier Transform
- 64-Pt Complex Fast Fourier Transform
- 256-Pt Complex Fast Fourier Transform
- 1024-Pt Complex Fast Fourier Transform
- All the features listed as being new with respect to the 64-256-1024-Pt Complex Fast Fourier Transform are also new with respect to these cores, plus:
- Run-time configurable transform point size
- Run-time configurable scaling schedule for scaled fixed-point
Bug Fixes
Known Issues