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AR# 29234

ML555 - What are the GTP locations for the PCI Express lanes?


Where can I obtain a UCF file for the ML555 board for use with PCI Express?


ES Silicon Board 
If you have an ES silicon board, the UCF for the Block Plus Wrapper for PCI Express can be found in the Block Plus Wrapper EA UCF file download. This is available in (Xilinx Answer 24697). The LX50T-FF1136-1 UCF in the UCF EA download has the correct pin locations for the ES ML555 Board. It also contains necessary placement constraints to meet timing on ES silicon. Along with this EA UCF file, the EA patch for the Block Plus Wrapper is also needed. For more information, see (Xilinx Answer 24697)
Production Silicon Board 
The Production silicon board has the same pin-outs as the ES silicon board. However, the logic placement constraints needed for ES silicon are not necessary in Production boards. To obtain the UCF file using CORE Generator, target the LX50T-FF1136-1 and generate the Block Plus Endpoint Wrapper.  
Once generated, in the example_design directory, open the provided UCF file and follow the instructions in (Xilinx Answer 31419) to modify the UCF file for the ML555 board.

Revision History
07/07/2010 - Updated to refer to (Xilinx Answer 31419).
AR# 29234
Date Created 09/04/2007
Last Updated 05/22/2014
Status Archive
Type General Article