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AR# 29242

14.x Release Note, Timing Analyzer - Order of constraints in PCF can produce different timing analyses


I notice that if the order of constraints in the PCF changes, my timing analysis gives different results. When I multiplex my clocks via BUFGMUX, this situation can happen based on the order of the constraints in the PCF.

How do I ensure that I obtain the same timing analysis in every implementation cycle?


The basic priority of similar constraints for similar paths is based on the order in the PCF. The higher priority constraints are later in the PCF. The last constraints might not always be the most critical constraints.

Similar constraints can have a PRIORITY constraint placed on them to force the timing tools to use the user-defined priorities. The PRIORITY keyword is used in the UCF when defining the constraint or specifying the priorities of the constraints. This works for multiplexed clocks but not for a clock derived by PLL/DCM/DLL components, as the constraints are automatically generated.

Since the constraints automatically generated by DCM/PLL/DLL components do not allow the PRIORITY constraint to be used, the following work-arounds are recommended:

1. You can add a PERIOD constraint on each output of the DLL/PLL/DCM component and not on the input. You can then decide the priority.

2. Modify the PCF to reorder the constraints. This has the disadvantage that the PCF will be regenerated every time you re-implement the design. If you place these constraints outside the SCHEMATIC START/END comments, the constraints will be removed only when running a "clean-up" project file.

For more details on timing constraints, please see the Timing Constraints User Guide: http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_1/ug612.pdf

AR# 29242
Date 11/12/2012
Status Active
Type Known Issues
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