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AR# 29246 LogiCORE FIFO Generator v4.2 - Release Notes and Known Issues for 9.2i SP3 IP Update 2 (9.2i_IP2)

Keywords: CORE, Generator, CORE Generator, IP, update, 9.2i, ip2_jm, FIFO, fifogen, asynchronous, synchronous, common, clocks, memory, block RAM, BRAM, RAMB16, FIFO16, asynch, asymmetric, non-symmetric, first, word, fall, through, fwft

This Release Note and Known Issues are for the FIFO Generator v4.2 Core released in 9.2i IP Update 2. It contains the following information:

- General Information
- New Features
- Bug Fixes
- Known Issues
- Device Issues

For installation instruction for IP Update 2, general CORE Generator known issues, and design tools requirements, see (Xilinx Answer 29185).

General Information
(Xilinx Answer 22014) When using FIFO Generator Core, the allowed data count width is less than it should be
(Xilinx Answer 22722) FIFO Generator Core now includes a User Guide in addition to a data sheet. Where can I find the User Guide for the FIFO Generator?
(Xilinx Answer 24712) How do I test user logic that triggers ECC SBITERR and DBITERR outputs in FIFO Generator?

New Features in v4.2
- Support for First-Word-Fall-Through read mode for Block RAM and Distributed RAM Common Clock FIFOs
- Option to not reset DOUT when reset signal is asserted

Bug Fixes in v4.2
(Xilinx Answer 29137) "WARNING:Ngdbuild:452 - logical net 'u1/BU2/prog_*_thresh_assert<*>' has no driver" - CR 431975
(Xilinx Answer 29173) In VHDL behavioral model simulation, DOUT powers up as 'x' until the first word is presented - CR 445849
(Xilinx Answer 29172) In behavioral model simulation, powerup values for DOUT and VALID are undefined - CR 445381
(Xilinx Answer 29228) Programmable Full and Empty flags do not work correctly when FIFO is full for Common Clock Block RAM and Distributed RAM FIFOs - CR 447282
- Write data count for Verilog behavior model reports incorrect and abnormally high values at or near empty (Independent Clock FIFOs only) - CR 448672
- Read data count behaves incorrectly when not at maximum width and FIFO is configured as First-Word-Fall-Through - CR 448521

Known Issues in v4.2
(Xilinx Answer 29513) In VHDL behavioral simulation UNDERFLOW flag does not work properly during RESET
(Xilinx Answer 29514) In Verilog behavioral simulation WR_DATA_COUNT is incorrect
(Xilinx Answer 29581) In Verilog behavioral simulation Programmable Full remains high after reset
(Xilinx Answer 24003) NCSIM warning seen when targeting Virtex-5
(Xilinx Answer 23691) Behavioral simulation models are not supported for built-in FIFO configuration
(Xilinx Answer 20291) During simulation: X_FF RECOVERY and SETUP warning can be seen
(Xilinx Answer 20271) Simulation Error is seen on RESET

FIFO Generator v4.1 Known Issues
-The FIFO Generator v4.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v4.1 issues, see (Xilinx Answer 25458).

FIFO Generator v3.3 Known Issues
-The FIFO Generator v3.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.3 issues, see (Xilinx Answer 24552).

FIFO Generator v3.2 Known Issues
-The FIFO Generator v3.2 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.2 issues, see (Xilinx Answer 23847).

FIFO Generator v3.1 Known Issues
-The FIFO Generator v3.1 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 23490).

FIFO Generator v2.3 Known Issues
-The FIFO Generator v2.3 is now obsolete. Please upgrade to the latest version of the core. For information on existing FIFO Generator v3.1 issues, see (Xilinx Answer 22302).
AR# 29246
Date Created
Last Updated 10/17/2007
Status Active
Type
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