This Release Note is for the Block Memory Generator Core v2.6 released in 9.2i IP Update 2. It contains the following information:
- General Information
- New Features
- Bug Fixes
- Known Issues
For installation instructions for IP Update 2 and design tools requirements, see (Xilinx Answer 29185).
The Xilinx Block Memory Generator v2.6 LogiCORE should be used in all new Virtex-5, Virtex-4 /-4 XA, Virtex-II, Virtex-II Pro, Spartan-II/E and Spartan-3 /-3E /-3E XA /-3A /-3 XA designs wherever a block memory is required. This core supersedes the Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores, but is not a direct drop-in replacement. A Block Memory Migration Kit is available on Xilinx.com to convert Single-Port Block Memory v6.2 and Dual-Port Block Memory v6.3 cores to the newer Block Memory Generator Core format.
See the Block Memory Core Migration Kit available at:
Also see (Xilinx Answer 24848) for known issues of the migration kit.
and (Xilinx Answer 29168) for changes made from pre-v2.4 XCO parameters.
A new Core Generator feature is available to upgrade the Block Memory Generator from v2.4 to the latest core. This feature is part of the CORE Generator and it is visible only if you open an existing CORE Generator project with a previously generated Block Memory Generator v2.4 core. See the "Upgrading a Core" section of the Core Generator User Guide (Software Manuals).
(Xilinx Answer 24712) How to test user logic that triggers ECC SBITERR and DBITERR outputs in the Block Memory Generator.
New Features in v2.6
Support for pipeline stages within the mux where applicable
Resolved Issues in v2.6
(Xilinx Answer 24804) Block Memory Generator GUI fails with an internal error if no value is entered for Write Depth - CR 432931
Known Issues in v2.6
(Xilinx Answer 24034) Core does not generate for large memories. Depending on the machine the CORE Generator runs on, the maximum size of the memory that can be generated will vary. For example, a Dual Pentium-4 server running at 3.6GHz with 2 Gig RAM can generate a memory core of a size 1.8 MBits or 230 K Bytes. - CR 415768
(Xilinx Answer 23744) Out-of-range address input can cause the core to generate X's on the DOUT bus.
(Xilinx Answer 24313) When using the core for Virtex-4 and Virtex-5 with Byte-write Enable and Write-First Operating Mode, the following warning might be displayed during simulation:
# ** Warning: Functional warning at simulation time ( 1572 ns)
: RAMB16( :top:bm_tb:test1_dut:bmg0:bmg0:bu2_u0_blk_mem_generator_
port A is in WRITE_FIRST mode requiring all bits of WEA to be all
'1's or all '0's to guarantee valid outputs.
# Time: 1572 ns Iteration: 3 Instance:
The Virtex-4 and Virtex-5 Errata is located at:
The Block Memory Generator Core is subject to all block RAM issues listed in the Errata.
Block Memory Generator v2.5 Known Issues
-The Block Memory Generator v2.5 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.5 issues, see (Xilinx Answer 25459).
Block Memory Generator v2.4 Known Issues
-The Block Memory Generator v2.4 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.4 issues, see (Xilinx Answer 24555).
Block Memory Generator v2.3 Known Issues
-The Block Memory Generator v2.3 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.3 issues, see (Xilinx Answer 24229).
Block Memory Generator v2.2 Known Issues
-The Block Memory Generator v2.2 is now obsolete. Please upgrade to the latest version of the core.
For information on existing Block Memory Generator v2.2 issues, see (Xilinx Answer 23849).