I have a design with a ChipScope core and am trying to probe a global clock net. The router is failing with the following message:
" WARNING:Route:436 - The router has detected an unroutable situation for one or more connections. The router will finish
the rest of the design and leave them as unrouted. The cause of this behavior is either an issue with the placement
or unroutable placement constraints. To allow you to use FPGA editor to isolate the problems, the following is a list
of (up to 10) such unroutable connections:
Unroutable signal: CLK0_CLKA1 pin: U_ila_pro_0/i_dt1/1/data_and_trig_dly1_3/BX
What can I do to correct this failure?
This problem can occur if a probe is added between a DCM/PLL output and a BUG due to routing resource limitations.
To correct for this, probe the BUFG output instead. Below is an example:
.CLK0 (CLK), // 0 degree DCM CLK output
.CLKFB (CLK_bufout) // DCM clock feedback
BUFG CLK_BUFG_INST (
To work around this problem, move the probe from CLK to CLK_bufout.