We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29296 System Generator for DSP - Why do I receive the error message "Design Rule Check Failed" when my DA FIR block uses a hardware oversampling value less than the sample period?


In the System Generator model, when I use the DA FIR block and set the hardware oversampling rate to an integer multiple of the Simulink system period and less than the blocks input and output rates, I receive a Design Rule Check violation.


This issue only affects designs using the DA FIR block with specific parameters as described below; none of the other FIR blocks are affected.

This DRC incorrectly flags legal combinations of input and output rates and the hardware oversampling rate. The DA FIR should accept all hardware oversampling rates that are equal to or less than the slower of the normalized input and output rates.

Currently, the DRC incorrectly flags non-integer relationships between the slower of the normalized input and output rates relative to the oversampling rate.

This is a known issue in System Generator 9.2.00 and will be resolved in the next release (9.2.01).

If this issue is affecting a DA FIR design and you cannot upgrade to the latest version of System Generator, a patch is available that resolves this known issue. You can download patch 968 for System Generator 9.2.00 at:


To install the patch, follow these steps:

1. Download sysgen9_2_00_968.zip.

2. Extract the zip file to a temporary location.

3. Launch MATLAB (if already open, close it and re-open.)

4. CD to the location the zip file was unzipped.

5. Run:


6. Restart MATLAB.

7. Run xlVersion to confirm the installation (the SysGen version should now be

AR# 29296
Date Created 10/28/2007
Last Updated 12/15/2012
Status Active
Type General Article