UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 29297

LogiCORE IP Cascaded Integrator Comb Compiler (CIC Compiler) - Release Notes and Known Issues

Description


This Answer Record contains the Release Notes and Known Issues list for the CIC Compiler Core. The following information is listed for each version of the core:
  • General Information
  • Supported Devices
  • New Features
  • Resolved Issues
  • Known Issues

For installation instructions for IP Update 1 and design tools requirements, see (Xilinx Answer 29185).

Solution


LogiCORE IP CIC Compiler v2.0

Initial Release in ISE Design Suite 12.1

New Features
  • ISE 12.1 software support
  • Support for Virtex-6Q and Spartan-6Q devices with ISE 12.1 software
  • Supports automatic core update from CIC Compiler v1.1, v1.2 and v1.3

Resolved Issue
  • CR 534532 Maximum output width for a programmable rate change interpolation filter should be based on the maximum rate rather than the minimum rate (Xilinx Answer 33573)
  • CR 537660 Filter output can become unstable following a rate change (Xilinx Answer 33733).

Known Issues
  • None

LogiCORE IP CIC Compiler v1.3

Initial Release in ISE Design Suite 11.3

New Features
  • ISE 11.3 software support
  • Virtex-6 and Spartan-6 device support added
  • Input and output streaming interface for multiple channel implementations
  • Resource sharing when the core is oversampled
  • Capability added to specify hardware oversampling specification as a sample period
  • Supports automatic core update from CIC Compiler v1.1 and CIC Compiler v1.2

Resolved Issues

Known Issues
  • (Xilinx Answer 33464) - CR 532603 - The behavioral model can issue an invalid error due to a check on the RATE port that it is within the valid range as specified in the GUI
  • (Xilinx Answer 33530) - Why is the output of my CIC Compiler block always undefined Xs in HDL Simulation or NAN's in System Generator?
  • (Xilinx Answer 33538) - Why does the data sheet installed with this core say "XILINX CONFIDENTIAL - INTERNAL"?
  • (Xilinx Answer 33573) - Why is the output width smaller than expected when a programmable rate change is used?
  • (Xilinx Answer 33733) - Why does the CIC overflow continually after applying a rate change to a programmable rate CIC?

LogiCORE IP CIC Compiler v1.2

Initial Release in ISE Design Suite 10.1 IP Update 0.

Resolved Issue
  • CR 449712 Simulation mismatches of CIC interpolator filters with NC-Sim

Known Issues
  • When implementing a programmable rate filter, I obtain incorrect results in a behavioral simulation when SCLR is not used. See (Xilinx Answer 30280).
  • Why do I see different behavior in post-PAR simulation compared to behavioral? Why do I receive incorrect results when I gate my input sample rate with the ND and CE signals? See (Xilinx Answer 31456).
  • Why do I receive Xs out during behavioral simulation while the RDY output is low? See (Xilinx Answer 30280).
  • Why does the CIC overflow continually after applying a rate change to a programmable rate CIC? (Xilinx Answer 33733)

LogiCORE IP CIC Compiler v1.1

Initial Release in ISE Design Suite 10.1 IP Update 0.

New Features
  • ISE 10.1 software support.

Resolved Issues
  • CR 453918 - Long core generation time for decimator filters with high rate change
  • CR 442008 - Missing latency and resource estimation values in GUI
  • CR 442008 - Incorrect scaling of attenuations in GUI Frequency Response Analysis

Known Issues
  • When implementing a programmable rate filter, I obtain incorrect results in a behavioral simulation when SCLR is not used. See (Xilinx Answer 30280).
  • Why are there mismatches between the behavioral simulation and the post-translate simulation, when using ISE Simulator, or NC-Sim with the CIC Compiler, DDS Compiler, or the Sine Cosine LUT IP? See (Xilinx Answer 30626).
  • Why does the CIC overflow continually after applying a rate change to a programmable rate CIC? (Xilinx Answer 33733) -

General Information

LogiCORE IP CIC Compiler v1.0

Initial Release in ISE Design Suite 9.2i IP Update 2.

New Features
  • None

Resolved Issues
  • None

Known Issues

General Information

Older CIC Filter cores

Cascaded Integrator Comb Filter v3.0
AR# 29297
Date Created 10/28/2007
Last Updated 06/20/2011
Status Active
Type Release Notes
IP
  • Cascaded Integrator Comb (CIC) Compiler