Solution

General Information
- MIG is no longer provided as a separate download, but is now incorporated into IP Updates. MIG v2.0 is available through 9.2i IP Update 2.

For a list of supported memory interfaces and maximum frequency support, see (Xilinx Answer 29446).

Software Requirements

- ISE 9.2i Service Pack 3.
- Synplify Pro 8.8.0.4 support.
- 32-bit Windows XP.
- 32-bit Linux Red Hat Enterprise 4.0 support.

New Features

General New Features and Changes
- 32-bit Linux Red Hat Enterprise 4.0 support.
- ML561 board designs include a PLL which can be used to synthesize different frequencies.
- Changed port and signal names to lower-case.
- Changed all parameters to upper-case.

Redesigned GUI Using Wizard Style
- Ease of use for parameter input and design generation.
- GUI frequency selection limits the available parameters to select.
- Memory parts are categorized into components, UDIMMs, SODIMMs, and RDIMMs.

Complete Simulation Environment
- Verilog/VHDL simulation test bench.
- ModelSim do script.
- Customized Micron memory model.
- Support for user-defined PCB delays in simulation test bench. This is not supported for Spartan-3 family DDR and DDR2 VHDL designs.

Modification of MIG Output Design Directory
- The "example_design" directory contains MIG design and synthesizable test bench (memory checker); previously titled "withtb" design.
- The "user_design" directory contains MIG design only; previously titled "withouttb" design.
- See the MIG v2.0 User Guide for further information.

Virtex-5 New Features and Changes

DDR2 SDRAM
- Support for SSTL Class I or Class II I/O Standard for Address and Control signals.
- Improved data capture timing using "DQS squelch circuit."
- 2T timing and ECC support.
- SODIMM and UDIMM support.
- Debug port; see (Xilinx Answer 29443).
- Improved timing requiring additional constraints; see (Xilinx Answer 29313).

DDR SDRAM
- DIMM support.

QDRII SRAM
- Clock signals K and K# are allocated to P-N pin pair.
- Limited support for Cascaded DCI.
- Added CQ# port.
- Allocation of 36-bit read data pins in one bank when using Cascaded DCI.

Virtex-4 New Features and Changes

DDR2 SDRAM
- Support for SSTL Class I or Class II I/O Standard for Address and Control signals.

QDRII SRAM
- Clock signals K and K# are allocated to a P-N pin pair.

Spartan-3, Spartan-3E, Spartan-3A New Features and Changes
- SODIMM support.

DDR2 SDRAM
- Support for SSTL Class I or Class II I/O Standard for Address and Control signals.

Resolved Issues

Virtex-5 Designs
- Reset signal for Registered DIMMs set to LVCMOS18 I/O Standard for Virtex-4 and Virtex-5 DDR2 designs
CR Number: CR 440103.
- MIG now generates one Data Mask port per x4 component for Virtex-5 DDR designs.
CR Number: 435696
Details: MIG properly generates one Data Mask port per x4 component for Virtex-5 DDR designs. Previously, one Data Mask signal was generated per eight bits.
- QDRII pin-out for Virtex-5 follows the rules required for CQ/CQ# capture.
CR Number: 440069
Details: CQ and CQ# are placed in the same bank.
- DCM DLL Frequency mode attribute is properly set for all frequency ranges for Virtex-5 designs.
CR Number: 443948
Details: Previously, this attribute was set incorrectly for frequencies below 150 MHz.
- ML561 Board files have the correct clock for the DDR2 DIMM and Component files.
CR Number: 440200.

Virtex-4 Designs
- Extended Mode Register option "DQS# Enable" available for multi controller Virtex-4 DDR2.
CR Number: 440104
Details: DDR2 Virtex-4 multi-controller designs will now set the different "DQS# Enable" selections properly in the generated code.
- Data Mask is properly applied when ECC is enabled for Virtex-4 DDR2 Direct Clocking designs.
CR Number: 445054
Details: Design previously applied a Data Mask set on a single byte from the user interface to two bytes on the DDR2 interface. Reset signal for Registered DIMMs set to LVCMOS18 I/O Standard for Virtex-4 and Virtex-5 DDR2 designs.
CR Number: CR 440103
- DDR2_RESET_N no longer tied high in Spartan-3 family and Virtex-4 DDR/DDR2 designs.
CR Number: 437672
Details: The DDR2_RESET_N signal is no longer tied High to allow the reset to be used to hold CKE=0 and the DQ bits in 3-state during power-up.
- Issuing Load Mode Register command from the User Interface properly sets new values in Virtex-4 Direct Clocking and SERDES designs.
CR Number: 434419
- Address bus does not oscillate during idle time for QDRII Burst Length=2 Virtex-4 designs.
CR Number: 437018
- RLDRAM II calibration will start after the memory initialization is completed.
CR Number: 437018
Details: Calibration previously started immediately following the 200 microsecond power up rather then waiting for the full initialization to complete.
- Correct address increment is included in the hardware test bench for the DDRII SRAM designs.
CR Number: 444367
- QDRII design for Virtex-4 no longer sends an extra read from the read address FIFO before the completion of calibration.
CR Number: 443947
- IOB = TRUE constraints embedded into RTL code for Virtex-4 and Spartan-3 family designs.
CR Number: 435769
Details: MIG now embeds the required IOB=TRUE constraints into the RTL code to force critical flops into the IOBs. This was completed for Virtex-4 and Spartan-3 family designs.

Spartan-3 Family Designs
- DDR2_RESET_N no longer tied high in Spartan-3 family and Virtex-4 DDR/DDR2 designs.
CR Number: 437672
Details: The DDR2_RESET_N signal is no longer tied High to allow the reset to be used to hold CKE=0 and the DQ bits in 3-state during power-up.
- IOB = TRUE constraints embedded into RTL code for Virtex-4 and Spartan-3 family designs.
CR Number: 435769
Details: MIG now embeds the required IOB=TRUE constraints into the RTL code to force critical flops into the IOBs. This was completed for Virtex-4 and Spartan-3 family designs.
- The number of "Write Pipe Stages" set in MIG are properly added to the test_bench module for Spartan-3 family DDR2 designs.
CR Number: 436871
- Common code implemented for different Burst Lengths and CAS Latencies for Spartan-3 family DDR designs.
CR Number: 429338
- Local clock routes are implemented correctly in all cases when top/bottom banks are selected for Spartan-3 family designs.
CR Number: 436873
Details: Changes to the UCF were made to specify the correct constraints.
- Removed unconstrained paths from Spartan-3 family designs.
CR Number: 306710

MIG Tool, Output, and Documentation
- Data Mask signals removed from Registered DIMMs that do not have Data Mask.
CR Number: 440102
- Added design options to the UCF file header.
CR Number: 443019

Known Issues
The following are known issues for v2.0 of this core. All of theses issues will be fixed in MIG v2.1.

Virtex-5 Designs
- The Virtex-5 DDR2 SDRAM design may encounter a set-up violation when CL=3 and AL=0 at low frequencies (typically below 200 MHz) because of the way the reference design is constrained.
CR Number: 455991
Work-around: See (Xilinx Answer 29900) for further information.
- The Virtex-5 DDR1 SDRAM interface passes calibration but read data is corrupted after calibration. This can occur either during simulation, and/or in actual hardware. If this phenomenon occurs, the last data word in a group of consecutive read bursts will be incorrect.
CR Number:452172
Work-around: See (Xilinx Answer 29903) for further information.
- The Virtex-5 DDR2 SDRAM controller incorrectly issues an ACTIVATE command to the previous row after completing an AUTO REFRESH. This will occur both in simulation and hardware.
CR Number: 453809
Work-around: See (Xilinx Answer 29783) for further information.
- The Virtex-5 DDR2 SDRAM design with ECC enabled for a 144-bit design has a data mask issue. The data mask will not work properly, and the simulation will fail with a fatal error. The issue exists in both Verilog and VHDL designs; however, only VHDL simulations fail.
CR Number: 449168
Work-around: See (Xilinx Answer 29478) for further information.
- Fatal out-of-bounds index error occurs when running a Virtex-5 DDR2 SDRAM VHDL simulation.
CR Number: 449166
Work-around: See (Xilinx Answer 29478) for further information.
- The UCF provided in the "user_design/par" directory of the Virtex-5 DDR2 SDRAM design will cause an error during MAP. The UCF is written for the multi-cycle paths within the example_design. MAP will fail on the CLK0_TB port.
- The Virtex-5 DDR SDRAM VHDL "user_design" simulation will fail with Syntax errors. The DM_WIDTH is defined in the generic port within the test bench component declaration; however, the parameter is not used.
CR Number: 450374
Work-around: Remove the DM_WIDTH parameter from the test bench component declaration.

Virtex-4 Designs
- MIG does not generate the Virtex-4 DDR SERDES Preset Configuration design when targeting the XC4V140-FF1517 device. Bank selection is not sufficient to generate the design.
CR Number: 440337
Work-around: Use the following parameters to generate the design using the "Create Design" feature within MIG:
Data width: 64 bit, Memory component: MT4V128M8XX-5B, Data banks: 5, 9, Address and System Control: 13, System Clock: 3.
- In the Virtex-4 DDR2 SDRAM Direct Clocking design, the user application signal APP_MASK_DATA is included in the user_design for all registered DIMMs. Some registered DIMMs do not have the data mask functionality and so this signal should not be used.
CR Number: 450380
- In the Virtex-4 RLDRAM II design, the user configuration commands do not work. The user configuration commands cannot be used.
CR Number: 449063

Spartan-3 Family Designs
- For all Spartan-3 families, the DDR/DDR2 design requires the loop back signal, rst_dqs_div, be allocated at the center of the DQ sets. MIG is not properly placing this signal at the center when top or bottom banks are selected or if Banks 2 or 3 are selected for the XC3S5000-FG900 device.
CR Number: 450334
Work-around: If the MAXDELAY constraint on the NET "main_00/top0/data_path0/data_read_controller0/rst_dqs_div" is met, the placement of the rst_dqs_div signal will not cause any issues.
- In the larger Spartan-3 devices, XC3S2000, XC3S4000, and XC3S5000, the local clock route delay when top or bottom banks are selected is larger than expected. Route delays are around 2425 ps instead of 1900 ps. This might fail in hardware. Left/Right bank selection is recommended for all larger Spartan-3 devices.
CR Number: 449062
Work-around: Select banks on either the left or right side of the device.
- Data Mask bits toggle between writes in the DDR2 design for Spartan-3 families.
CR Number: 432159
- MIG does not generate the Preset Configuration for the XC3S50CP132 device.
CR Number: 450338
- The BL=8 DDR_SDRAM design running at 166 MHz will fail in simulation with Twr violations. Both Verilog and VHDL designs have this issue.
CR Number: 450373
- The DDR SDRAM design targeting a RDIMM with VHDL does not drive the clk_tb signal in the "user_design." The following statement is incorrectly commented:
signal clk_tb <= clk_int after 1 ps;
CR Number: 450376
- The slice_packing option within XST should be set to false. This will result in better timing.
CR Number: 450382

MIG Tool, Output, and Documentation
- Memory models provided by MIG are not the latest available.
CR Number: 450381
Work-around: To use the latest models, download the required model from the memory vendors Web site and then refer to the "simulation_help.chm" help file located in the "sim" directory of the generated design for information on replacing the provided model with the newly downloaded model.
- When using the "Create New Memory Part" feature, the memory model provided in the "sim" directory might not be compatible with the custom part. It will be compatible with the selected base part.
CR Number: 448077
Work-around: Edit the memory parameter file manually to set the correct parameters.
- The default MIG setting for Spartan-3 family designs will not generate when smaller Spartan-3 devices are selected. Selecting more banks is required for MIG to generate the design.
- When DCI is selected for Virtex-4 and Virtex-5 designs, the WASSO Limit and Available I/Os are not decreased due to needed usage of the VRN and VRP pins.
- If WASSO Limits are entered on the Bank Selection GUI screen for Virtex-4 and Virtex-5 designs, the limits are not retained if the user navigates to a previous screen and then returns to the Bank Selection screen.
- In the Virtex-4 RLDRAMII(CIO) and DDRII SRAM designs, the WASSO limit specified in the GUI is applied to all signals in the bank regardless of input, input and output. WASSO should be applied to only input and output signals.
CR Number: 450380
- MIG sets the frequency of the Virtex-4 RLDRAMII design independent of the configuration value.
CR Number: 449064
Work-around: Manually set the frequency according to the selected memory configuration.
- When the Virtex-4 RLDRAMII design's Address Mux parameter is set to Multiplexed, the MIG GUI shows the incorrect number of address pins in the bank selection window. The window shows the number of pins required for a Non-Multiplexed Address. The design will be generated with the correct number of address pins.
- The MIG v2.0 User Guide does not include the supported RDIMMs, SODIMMs, and UDIMMs for Virtex-5 DDR in Table 11-6: Supported Devices for DDR SDRAM
CR Number: 450377
- The MIG v2.0 User Guide in some locations incorrectly refers to "withtb" and "withouttb" designs. This is from previous releases of MIG. The designs are now called "user_design" (withouttb) and "example_design" (withtb).
- The MIG v2.0 User Guide "MIG 2.0 Changes from MIG 1.73" section lists "Supports timing verified designs." This should instead state "Supports preset configuration designs."
CR Number: 450379